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net: phy: aquantia: only poll GLOBAL_CFG regs on aqr113, aqr113c and aqr115c 

JIRA: https://issues.redhat.com/browse/RHEL-57766

commit a7f3abcf635767b2e19c4c55c4c35756595ebc86
Author: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Date:   Mon Jul 29 17:03:14 2024 +0200

    net: phy: aquantia: only poll GLOBAL_CFG regs on aqr113, aqr113c and aqr115c

    Commit 708405f3e56e ("net: phy: aquantia: wait for the GLOBAL_CFG to
    start returning real values") introduced a workaround for an issue
    observed on aqr115c. However there were never any reports of it
    happening on other models and the workaround has been reported to cause
    and issue on aqr113c (and it may cause the same on any other model not
    supporting 10M mode).

    Let's limit the impact of the workaround to aqr113, aqr113c and aqr115c
    and poll the 100M GLOBAL_CFG register instead as both models are known
    to support it correctly.

    Reported-by: Jon Hunter <jonathanh@nvidia.com>
    Closes: https://lore.kernel.org/lkml/7c0140be-4325-4005-9068-7e0fc5ff344d@nvidia.com/
    Fixes: 708405f3e56e ("net: phy: aquantia: wait for the GLOBAL_CFG to start returning real values")
    Tested-by: Jon Hunter <jonathanh@nvidia.com>
    Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
    Reviewed-by: Antoine Tenart <atenart@kernel.org>
    Link: https://patch.msgid.link/20240729150315.65798-1-brgl@bgdev.pl
    Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Signed-off-by: Izabela Bakollari <ibakolla@redhat.com>
This commit is contained in:
Izabela Bakollari 2024-11-26 13:03:01 +01:00
parent 1d9532ca99
commit 4b4c84c5cd
1 changed files with 21 additions and 8 deletions
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29
drivers/net/phy/aquantia/aquantia_main.c
View File

@ -663,13 +663,7 @@ static int aqr107_fill_interface_modes(struct phy_device *phydev)
unsigned long *possible = phydev->possible_interfaces;
unsigned int serdes_mode, rate_adapt;
phy_interface_t interface;
int i, val, ret;
ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
VEND1_GLOBAL_CFG_10M, val, val != 0,
1000, 100000, false);
if (ret)
return ret;
int i, val;
/* Walk the media-speed configuration registers to determine which
* host-side serdes modes may be used by the PHY depending on the
@ -718,6 +712,25 @@ static int aqr107_fill_interface_modes(struct phy_device *phydev)
return 0;
}
static int aqr113c_fill_interface_modes(struct phy_device *phydev)
{
int val, ret;
/* It's been observed on some models that - when coming out of suspend
* - the FW signals that the PHY is ready but the GLOBAL_CFG registers
* continue on returning zeroes for some time. Let's poll the 100M
* register until it returns a real value as both 113c and 115c support
* this mode.
*/
ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
VEND1_GLOBAL_CFG_100M, val, val != 0,
1000, 100000, false);
if (ret)
return ret;
return aqr107_fill_interface_modes(phydev);
}
static int aqr113c_config_init(struct phy_device *phydev)
{
int ret;
@ -735,7 +748,7 @@ static int aqr113c_config_init(struct phy_device *phydev)
if (ret)
return ret;
return aqr107_fill_interface_modes(phydev);
return aqr113c_fill_interface_modes(phydev);
}
static int aqr107_probe(struct phy_device *phydev)