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PCI: qcom: Fix the incorrect register usage in v2.7.0 config 

Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2228915
Upstream Status: 2542e16c392508800f1d9037feee881a9c444951

commit 2542e16c392508800f1d9037feee881a9c444951
Author: Manivannan Sadhasivam <mani@kernel.org>
Date:   Thu Mar 16 13:40:59 2023 +0530

    PCI: qcom: Fix the incorrect register usage in v2.7.0 config

    Qcom PCIe IP version v2.7.0 and its derivatives don't contain the
    PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT register. Instead, they have the new
    PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 register. So fix the incorrect
    register usage which is modifying a different register.

    Also in this IP version, this register change doesn't depend on MSI
    being enabled. So remove that check also.

    Link: https://lore.kernel.org/r/20230316081117.14288-2-manivannan.sadhasivam@linaro.org
    Fixes: ed8cc3b1fc ("PCI: qcom: Add support for SDM845 PCIe controller")
    Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
    Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
    Cc: <stable@vger.kernel.org> # 5.6+

Signed-off-by: Myron Stowe <mstowe@redhat.com>
This commit is contained in:
Myron Stowe 2023-08-01 18:43:54 -06:00
parent baacac4dbf
commit 1fa781a8f0
1 changed files with 3 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/pci/controller/dwc/pcie-qcom.c
View File

@ -1279,11 +1279,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
val &= ~REQ_NOT_ENTR_L1;
writel(val, pcie->parf + PCIE20_PARF_PM_CTRL);
if (IS_ENABLED(CONFIG_PCI_MSI)) {
val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
val |= BIT(31);
writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
}
val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
val |= BIT(31);
writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
return 0;
err_disable_clocks: