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clocksource/drivers/arm_arch_timer: Extend write side of timer register accessors to u64 

Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2167398

commit 1e8d929231cf7b397101c5e6aaaa3d9bc9832f10
Author: Marc Zyngier <maz@kernel.org>
Date: Sun, 17 Oct 2021 13:42:11 +0100

    The various accessors for the timer sysreg and MMIO registers are
    currently hardwired to 32bit. However, we are about to introduce
    the use of the CVAL registers, which require a 64bit access.

    Upgrade the write side of the accessors to take a 64bit value
    (the read side is left untouched as we don't plan to ever read
    back any of these registers).

    No functional change expected.

    Reviewed-by: Oliver Upton <oupton@google.com>
    Reviewed-by: Mark Rutland <mark.rutland@arm.com>
    Tested-by: Mark Rutland <mark.rutland@arm.com>
    Signed-off-by: Marc Zyngier <maz@kernel.org>
    Link: https://lore.kernel.org/r/20211017124225.3018098-4-maz@kernel.org
    Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Signed-off-by: Mark Salter <msalter@redhat.com>
This commit is contained in:
Mark Salter 2023-02-08 09:14:04 -05:00
parent b53ae78da2
commit 02eae6659e
3 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/include/asm/arch_timer.h
View File

@ -24,15 +24,15 @@ int arch_timer_arch_init(void);
* the code. At least it does so with a recent GCC (4.6.3).
*/
static __always_inline
void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
{
if (access == ARCH_TIMER_PHYS_ACCESS) {
switch (reg) {
case ARCH_TIMER_REG_CTRL:
asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" ((u32)val));
break;
case ARCH_TIMER_REG_TVAL:
asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" ((u32)val));
break;
default:
BUILD_BUG();
@ -40,10 +40,10 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
} else if (access == ARCH_TIMER_VIRT_ACCESS) {
switch (reg) {
case ARCH_TIMER_REG_CTRL:
asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" ((u32)val));
break;
case ARCH_TIMER_REG_TVAL:
asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" ((u32)val));
break;
default:
BUILD_BUG();

2
arch/arm64/include/asm/arch_timer.h
View File

@ -89,7 +89,7 @@ static inline notrace u64 arch_timer_read_cntvct_el0(void)
* the code.
*/
static __always_inline
void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
{
if (access == ARCH_TIMER_PHYS_ACCESS) {
switch (reg) {

10
drivers/clocksource/arm_arch_timer.c
View File

@ -100,17 +100,17 @@ early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
*/
static __always_inline
void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,
struct clock_event_device *clk)
{
if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
struct arch_timer *timer = to_arch_timer(clk);
switch (reg) {
case ARCH_TIMER_REG_CTRL:
writel_relaxed(val, timer->base + CNTP_CTL);
writel_relaxed((u32)val, timer->base + CNTP_CTL);
break;
case ARCH_TIMER_REG_TVAL:
writel_relaxed(val, timer->base + CNTP_TVAL);
writel_relaxed((u32)val, timer->base + CNTP_TVAL);
break;
default:
BUILD_BUG();
@ -119,10 +119,10 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
struct arch_timer *timer = to_arch_timer(clk);
switch (reg) {
case ARCH_TIMER_REG_CTRL:
writel_relaxed(val, timer->base + CNTV_CTL);
writel_relaxed((u32)val, timer->base + CNTV_CTL);
break;
case ARCH_TIMER_REG_TVAL:
writel_relaxed(val, timer->base + CNTV_TVAL);
writel_relaxed((u32)val, timer->base + CNTV_TVAL);
break;
default:
BUILD_BUG();