2019-05-19 13:51:31 +00:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2013-03-22 14:34:03 +00:00
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/*
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* Copyright (c) 2009-2013, NVIDIA Corporation. All rights reserved.
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*/
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#ifndef __LINUX_HOST1X_H
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#define __LINUX_HOST1X_H
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2013-10-14 12:43:22 +00:00
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#include <linux/device.h>
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2022-11-29 04:32:53 +00:00
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#include <linux/dma-direction.h>
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2023-05-05 04:48:21 +00:00
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#include <linux/dma-fence.h>
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2022-11-29 04:34:28 +00:00
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#include <linux/spinlock.h>
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2013-09-24 14:30:32 +00:00
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#include <linux/types.h>
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2013-03-22 14:34:03 +00:00
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enum host1x_class {
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2013-09-24 11:59:01 +00:00
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HOST1X_CLASS_HOST1X = 0x1,
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HOST1X_CLASS_GR2D = 0x51,
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HOST1X_CLASS_GR2D_SB = 0x52,
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2016-12-14 11:16:13 +00:00
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HOST1X_CLASS_VIC = 0x5D,
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2013-02-28 07:08:01 +00:00
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HOST1X_CLASS_GR3D = 0x60,
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2022-11-29 04:38:01 +00:00
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HOST1X_CLASS_NVDEC = 0xF0,
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HOST1X_CLASS_NVDEC1 = 0xF5,
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2013-03-22 14:34:03 +00:00
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};
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2020-03-25 20:16:03 +00:00
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struct host1x;
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2013-09-24 13:35:40 +00:00
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struct host1x_client;
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2019-02-08 13:35:13 +00:00
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struct iommu_group;
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2013-09-24 13:35:40 +00:00
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2020-03-25 20:16:03 +00:00
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u64 host1x_get_dma_mask(struct host1x *host1x);
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2022-11-29 04:34:28 +00:00
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/**
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* struct host1x_bo_cache - host1x buffer object cache
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* @mappings: list of mappings
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* @lock: synchronizes accesses to the list of mappings
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2022-12-06 07:00:31 +00:00
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*
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* Note that entries are not periodically evicted from this cache and instead need to be
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* explicitly released. This is used primarily for DRM/KMS where the cache's reference is
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* released when the last reference to a buffer object represented by a mapping in this
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* cache is dropped.
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2022-11-29 04:34:28 +00:00
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*/
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struct host1x_bo_cache {
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struct list_head mappings;
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struct mutex lock;
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};
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static inline void host1x_bo_cache_init(struct host1x_bo_cache *cache)
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{
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INIT_LIST_HEAD(&cache->mappings);
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mutex_init(&cache->lock);
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}
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static inline void host1x_bo_cache_destroy(struct host1x_bo_cache *cache)
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{
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/* XXX warn if not empty? */
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mutex_destroy(&cache->lock);
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}
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2017-04-10 10:27:01 +00:00
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/**
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* struct host1x_client_ops - host1x client operations
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2021-03-26 14:51:37 +00:00
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* @early_init: host1x client early initialization code
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2017-04-10 10:27:01 +00:00
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* @init: host1x client initialization code
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* @exit: host1x client tear down code
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2021-03-26 14:51:37 +00:00
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* @late_exit: host1x client late tear down code
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2019-12-02 14:29:03 +00:00
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* @suspend: host1x client suspend code
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* @resume: host1x client resume code
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2017-04-10 10:27:01 +00:00
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*/
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2013-09-24 13:35:40 +00:00
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struct host1x_client_ops {
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2021-03-26 14:51:37 +00:00
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int (*early_init)(struct host1x_client *client);
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2013-09-24 13:35:40 +00:00
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int (*init)(struct host1x_client *client);
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int (*exit)(struct host1x_client *client);
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2021-03-26 14:51:37 +00:00
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int (*late_exit)(struct host1x_client *client);
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2019-12-02 14:29:03 +00:00
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int (*suspend)(struct host1x_client *client);
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int (*resume)(struct host1x_client *client);
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2013-09-24 13:35:40 +00:00
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};
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2017-04-10 10:27:01 +00:00
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/**
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* struct host1x_client - host1x client structure
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* @list: list node for the host1x client
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2019-12-02 09:51:58 +00:00
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* @host: pointer to struct device representing the host1x controller
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2017-04-10 10:27:01 +00:00
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* @dev: pointer to struct device backing this host1x client
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2019-02-08 13:35:13 +00:00
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* @group: IOMMU group that this client is a member of
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2017-04-10 10:27:01 +00:00
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* @ops: host1x client operations
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* @class: host1x class represented by this client
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* @channel: host1x channel associated with this client
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* @syncpts: array of syncpoints requested for this client
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* @num_syncpts: number of syncpoints requested for this client
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2020-06-14 04:08:04 +00:00
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* @parent: pointer to parent structure
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* @usecount: reference count for this structure
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* @lock: mutex for mutually exclusive concurrency
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2023-01-06 11:51:08 +00:00
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* @cache: host1x buffer object cache
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2017-04-10 10:27:01 +00:00
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*/
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2013-09-24 13:35:40 +00:00
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struct host1x_client {
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struct list_head list;
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2019-12-02 09:51:58 +00:00
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struct device *host;
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2013-09-24 13:35:40 +00:00
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struct device *dev;
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2019-02-08 13:35:13 +00:00
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struct iommu_group *group;
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2013-09-24 13:35:40 +00:00
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const struct host1x_client_ops *ops;
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enum host1x_class class;
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struct host1x_channel *channel;
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struct host1x_syncpt **syncpts;
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unsigned int num_syncpts;
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2019-12-02 14:29:03 +00:00
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struct host1x_client *parent;
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unsigned int usecount;
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struct mutex lock;
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2022-11-29 04:34:28 +00:00
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struct host1x_bo_cache cache;
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2013-09-24 13:35:40 +00:00
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};
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2013-09-24 14:30:32 +00:00
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/*
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* host1x buffer objects
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*/
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struct host1x_bo;
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struct sg_table;
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2022-11-29 04:32:53 +00:00
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struct host1x_bo_mapping {
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2022-11-29 04:34:28 +00:00
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struct kref ref;
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2022-11-29 04:32:53 +00:00
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struct dma_buf_attachment *attach;
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enum dma_data_direction direction;
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2022-11-29 04:34:28 +00:00
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struct list_head list;
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2022-11-29 04:32:53 +00:00
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struct host1x_bo *bo;
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struct sg_table *sgt;
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unsigned int chunks;
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struct device *dev;
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dma_addr_t phys;
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size_t size;
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2022-11-29 04:34:28 +00:00
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struct host1x_bo_cache *cache;
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struct list_head entry;
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2022-11-29 04:32:53 +00:00
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};
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2022-11-29 04:34:28 +00:00
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static inline struct host1x_bo_mapping *to_host1x_bo_mapping(struct kref *ref)
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{
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return container_of(ref, struct host1x_bo_mapping, ref);
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}
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2013-09-24 14:30:32 +00:00
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struct host1x_bo_ops {
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struct host1x_bo *(*get)(struct host1x_bo *bo);
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void (*put)(struct host1x_bo *bo);
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2022-11-29 04:32:53 +00:00
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struct host1x_bo_mapping *(*pin)(struct device *dev, struct host1x_bo *bo,
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enum dma_data_direction dir);
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void (*unpin)(struct host1x_bo_mapping *map);
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2013-09-24 14:30:32 +00:00
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void *(*mmap)(struct host1x_bo *bo);
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void (*munmap)(struct host1x_bo *bo, void *addr);
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};
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struct host1x_bo {
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const struct host1x_bo_ops *ops;
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2022-11-29 04:34:28 +00:00
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struct list_head mappings;
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spinlock_t lock;
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2013-09-24 14:30:32 +00:00
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};
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static inline void host1x_bo_init(struct host1x_bo *bo,
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const struct host1x_bo_ops *ops)
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{
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2022-11-29 04:34:28 +00:00
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INIT_LIST_HEAD(&bo->mappings);
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spin_lock_init(&bo->lock);
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2013-09-24 14:30:32 +00:00
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bo->ops = ops;
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}
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static inline struct host1x_bo *host1x_bo_get(struct host1x_bo *bo)
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{
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return bo->ops->get(bo);
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}
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static inline void host1x_bo_put(struct host1x_bo *bo)
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{
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bo->ops->put(bo);
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}
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2022-11-29 04:34:28 +00:00
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struct host1x_bo_mapping *host1x_bo_pin(struct device *dev, struct host1x_bo *bo,
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enum dma_data_direction dir,
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struct host1x_bo_cache *cache);
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void host1x_bo_unpin(struct host1x_bo_mapping *map);
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2013-09-24 14:30:32 +00:00
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static inline void *host1x_bo_mmap(struct host1x_bo *bo)
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{
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return bo->ops->mmap(bo);
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}
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static inline void host1x_bo_munmap(struct host1x_bo *bo, void *addr)
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{
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bo->ops->munmap(bo, addr);
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}
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/*
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* host1x syncpoints
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*/
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2013-10-14 12:21:52 +00:00
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#define HOST1X_SYNCPT_CLIENT_MANAGED (1 << 0)
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2013-10-14 12:21:53 +00:00
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#define HOST1X_SYNCPT_HAS_BASE (1 << 1)
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2013-10-14 12:21:52 +00:00
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2013-10-14 12:21:53 +00:00
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struct host1x_syncpt_base;
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2013-09-24 14:30:32 +00:00
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struct host1x_syncpt;
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struct host1x;
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2021-03-29 13:38:32 +00:00
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struct host1x_syncpt *host1x_syncpt_get_by_id(struct host1x *host, u32 id);
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struct host1x_syncpt *host1x_syncpt_get_by_id_noref(struct host1x *host, u32 id);
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struct host1x_syncpt *host1x_syncpt_get(struct host1x_syncpt *sp);
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2013-09-24 14:30:32 +00:00
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u32 host1x_syncpt_id(struct host1x_syncpt *sp);
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u32 host1x_syncpt_read_min(struct host1x_syncpt *sp);
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u32 host1x_syncpt_read_max(struct host1x_syncpt *sp);
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2015-01-28 13:29:02 +00:00
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u32 host1x_syncpt_read(struct host1x_syncpt *sp);
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2013-09-24 14:30:32 +00:00
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int host1x_syncpt_incr(struct host1x_syncpt *sp);
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2014-02-19 22:48:36 +00:00
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u32 host1x_syncpt_incr_max(struct host1x_syncpt *sp, u32 incrs);
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2013-09-24 14:30:32 +00:00
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int host1x_syncpt_wait(struct host1x_syncpt *sp, u32 thresh, long timeout,
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u32 *value);
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2017-08-30 10:48:31 +00:00
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struct host1x_syncpt *host1x_syncpt_request(struct host1x_client *client,
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2013-10-14 12:21:52 +00:00
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unsigned long flags);
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2021-03-29 13:38:32 +00:00
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void host1x_syncpt_put(struct host1x_syncpt *sp);
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2021-03-29 13:38:28 +00:00
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struct host1x_syncpt *host1x_syncpt_alloc(struct host1x *host,
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unsigned long flags,
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const char *name);
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2013-09-24 14:30:32 +00:00
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2013-10-14 12:21:53 +00:00
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struct host1x_syncpt_base *host1x_syncpt_get_base(struct host1x_syncpt *sp);
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u32 host1x_syncpt_base_id(struct host1x_syncpt_base *base);
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2021-03-29 13:38:34 +00:00
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void host1x_syncpt_release_vblank_reservation(struct host1x_client *client,
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u32 syncpt_id);
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2023-05-05 04:48:21 +00:00
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struct dma_fence *host1x_fence_create(struct host1x_syncpt *sp, u32 threshold,
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bool timeout);
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void host1x_fence_cancel(struct dma_fence *fence);
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2022-11-26 05:18:21 +00:00
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2013-09-24 14:30:32 +00:00
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/*
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* host1x channel
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*/
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struct host1x_channel;
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struct host1x_job;
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2018-06-18 12:01:51 +00:00
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struct host1x_channel *host1x_channel_request(struct host1x_client *client);
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2013-09-24 14:30:32 +00:00
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struct host1x_channel *host1x_channel_get(struct host1x_channel *channel);
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2022-11-29 05:15:46 +00:00
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void host1x_channel_stop(struct host1x_channel *channel);
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2013-09-24 14:30:32 +00:00
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void host1x_channel_put(struct host1x_channel *channel);
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int host1x_job_submit(struct host1x_job *job);
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/*
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* host1x job
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*/
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2019-10-28 12:37:11 +00:00
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#define HOST1X_RELOC_READ (1 << 0)
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#define HOST1X_RELOC_WRITE (1 << 1)
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2013-09-24 14:30:32 +00:00
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struct host1x_reloc {
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2014-06-10 08:25:00 +00:00
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struct {
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struct host1x_bo *bo;
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unsigned long offset;
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} cmdbuf;
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struct {
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struct host1x_bo *bo;
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unsigned long offset;
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} target;
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unsigned long shift;
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2019-10-28 12:37:11 +00:00
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unsigned long flags;
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2013-09-24 14:30:32 +00:00
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};
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struct host1x_job {
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/* When refcount goes to zero, job can be freed */
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struct kref ref;
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/* List entry */
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struct list_head list;
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/* Channel where job is submitted to */
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struct host1x_channel *channel;
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2018-05-16 12:12:33 +00:00
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/* client where the job originated */
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struct host1x_client *client;
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2013-09-24 14:30:32 +00:00
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/* Gathers and their memory */
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2022-11-26 05:47:15 +00:00
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struct host1x_job_cmd *cmds;
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unsigned int num_cmds;
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2013-09-24 14:30:32 +00:00
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/* Array of handles to be pinned & unpinned */
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2018-05-16 14:58:44 +00:00
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struct host1x_reloc *relocs;
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2013-09-24 14:30:32 +00:00
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unsigned int num_relocs;
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struct host1x_job_unpin_data *unpins;
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unsigned int num_unpins;
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dma_addr_t *addr_phys;
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dma_addr_t *gather_addr_phys;
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dma_addr_t *reloc_addr_phys;
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/* Sync point id, number of increments and end related to the submit */
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2021-03-29 13:38:32 +00:00
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struct host1x_syncpt *syncpt;
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2013-09-24 14:30:32 +00:00
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|
u32 syncpt_incrs;
|
|
|
|
u32 syncpt_end;
|
|
|
|
|
2023-05-05 04:48:21 +00:00
|
|
|
/* Completion fence for job tracking */
|
|
|
|
struct dma_fence *fence;
|
|
|
|
struct dma_fence_cb fence_cb;
|
gpu: host1x: Add no-recovery mode
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2154295
Upstream Status: v5.15-rc1
commit c78f837ae3d1e532ff4eb90155b42d7a2e892a3f
Author: Mikko Perttunen <mperttunen@nvidia.com>
AuthorDate: Thu Jun 10 14:04:43 2021 +0300
Commit: Thierry Reding <treding@nvidia.com>
CommitDate: Tue Aug 10 14:40:23 2021 +0200
Add a new property for jobs to enable or disable recovery i.e.
CPU increments of syncpoints to max value on job timeout. This
allows for a more solid model for hanged jobs, where userspace
doesn't need to guess if a syncpoint increment happened because
the job completed, or because job timeout was triggered.
On job timeout, we stop the channel, NOP all future jobs on the
channel using the same syncpoint, mark the syncpoint as locked
and resume the channel from the next job, if any.
The future jobs are NOPed, since because we don't do the CPU
increments, the value of the syncpoint is no longer synchronized,
and any waiters would become confused if a future job incremented
the syncpoint. The syncpoint is marked locked to ensure that any
future jobs cannot increment the syncpoint either, until the
application has recognized the situation and reallocated the
syncpoint.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2022-11-26 05:02:17 +00:00
|
|
|
|
2013-09-24 14:30:32 +00:00
|
|
|
/* Maximum time to wait for this job */
|
|
|
|
unsigned int timeout;
|
|
|
|
|
gpu: host1x: Add no-recovery mode
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2154295
Upstream Status: v5.15-rc1
commit c78f837ae3d1e532ff4eb90155b42d7a2e892a3f
Author: Mikko Perttunen <mperttunen@nvidia.com>
AuthorDate: Thu Jun 10 14:04:43 2021 +0300
Commit: Thierry Reding <treding@nvidia.com>
CommitDate: Tue Aug 10 14:40:23 2021 +0200
Add a new property for jobs to enable or disable recovery i.e.
CPU increments of syncpoints to max value on job timeout. This
allows for a more solid model for hanged jobs, where userspace
doesn't need to guess if a syncpoint increment happened because
the job completed, or because job timeout was triggered.
On job timeout, we stop the channel, NOP all future jobs on the
channel using the same syncpoint, mark the syncpoint as locked
and resume the channel from the next job, if any.
The future jobs are NOPed, since because we don't do the CPU
increments, the value of the syncpoint is no longer synchronized,
and any waiters would become confused if a future job incremented
the syncpoint. The syncpoint is marked locked to ensure that any
future jobs cannot increment the syncpoint either, until the
application has recognized the situation and reallocated the
syncpoint.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2022-11-26 05:02:17 +00:00
|
|
|
/* Job has timed out and should be released */
|
|
|
|
bool cancelled;
|
|
|
|
|
2013-09-24 14:30:32 +00:00
|
|
|
/* Index and number of slots used in the push buffer */
|
|
|
|
unsigned int first_get;
|
|
|
|
unsigned int num_slots;
|
|
|
|
|
|
|
|
/* Copy of gathers */
|
|
|
|
size_t gather_copy_size;
|
|
|
|
dma_addr_t gather_copy;
|
|
|
|
u8 *gather_copy_mapped;
|
|
|
|
|
|
|
|
/* Check if register is marked as an address reg */
|
2017-06-14 23:18:38 +00:00
|
|
|
int (*is_addr_reg)(struct device *dev, u32 class, u32 reg);
|
2013-09-24 14:30:32 +00:00
|
|
|
|
2017-06-14 23:18:37 +00:00
|
|
|
/* Check if class belongs to the unit */
|
|
|
|
int (*is_valid_class)(u32 class);
|
|
|
|
|
2013-09-24 14:30:32 +00:00
|
|
|
/* Request a SETCLASS to this class */
|
|
|
|
u32 class;
|
|
|
|
|
|
|
|
/* Add a channel wait for previous ops to complete */
|
|
|
|
bool serialize;
|
gpu: host1x: Add no-recovery mode
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2154295
Upstream Status: v5.15-rc1
commit c78f837ae3d1e532ff4eb90155b42d7a2e892a3f
Author: Mikko Perttunen <mperttunen@nvidia.com>
AuthorDate: Thu Jun 10 14:04:43 2021 +0300
Commit: Thierry Reding <treding@nvidia.com>
CommitDate: Tue Aug 10 14:40:23 2021 +0200
Add a new property for jobs to enable or disable recovery i.e.
CPU increments of syncpoints to max value on job timeout. This
allows for a more solid model for hanged jobs, where userspace
doesn't need to guess if a syncpoint increment happened because
the job completed, or because job timeout was triggered.
On job timeout, we stop the channel, NOP all future jobs on the
channel using the same syncpoint, mark the syncpoint as locked
and resume the channel from the next job, if any.
The future jobs are NOPed, since because we don't do the CPU
increments, the value of the syncpoint is no longer synchronized,
and any waiters would become confused if a future job incremented
the syncpoint. The syncpoint is marked locked to ensure that any
future jobs cannot increment the syncpoint either, until the
application has recognized the situation and reallocated the
syncpoint.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2022-11-26 05:02:17 +00:00
|
|
|
|
|
|
|
/* Fast-forward syncpoint increments on job timeout */
|
|
|
|
bool syncpt_recovery;
|
2022-11-26 05:23:26 +00:00
|
|
|
|
|
|
|
/* Callback called when job is freed */
|
|
|
|
void (*release)(struct host1x_job *job);
|
|
|
|
void *user_data;
|
2022-11-26 05:24:04 +00:00
|
|
|
|
|
|
|
/* Whether host1x-side firewall should be ran for this job or not */
|
|
|
|
bool enable_firewall;
|
2022-12-06 07:12:38 +00:00
|
|
|
|
|
|
|
/* Options for configuring engine data stream ID */
|
|
|
|
/* Context device to use for job */
|
|
|
|
struct host1x_memory_context *memory_context;
|
|
|
|
/* Stream ID to use if context isolation is disabled (!memory_context) */
|
|
|
|
u32 engine_fallback_streamid;
|
|
|
|
/* Engine offset to program stream ID to */
|
|
|
|
u32 engine_streamid_offset;
|
2013-09-24 14:30:32 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
struct host1x_job *host1x_job_alloc(struct host1x_channel *ch,
|
2022-11-26 05:24:04 +00:00
|
|
|
u32 num_cmdbufs, u32 num_relocs,
|
|
|
|
bool skip_firewall);
|
2018-05-16 15:01:43 +00:00
|
|
|
void host1x_job_add_gather(struct host1x_job *job, struct host1x_bo *bo,
|
|
|
|
unsigned int words, unsigned int offset);
|
2022-11-26 05:47:15 +00:00
|
|
|
void host1x_job_add_wait(struct host1x_job *job, u32 id, u32 thresh,
|
|
|
|
bool relative, u32 next_class);
|
2013-09-24 14:30:32 +00:00
|
|
|
struct host1x_job *host1x_job_get(struct host1x_job *job);
|
|
|
|
void host1x_job_put(struct host1x_job *job);
|
|
|
|
int host1x_job_pin(struct host1x_job *job, struct device *dev);
|
|
|
|
void host1x_job_unpin(struct host1x_job *job);
|
|
|
|
|
2013-10-14 12:43:22 +00:00
|
|
|
/*
|
|
|
|
* subdevice probe infrastructure
|
|
|
|
*/
|
|
|
|
|
|
|
|
struct host1x_device;
|
|
|
|
|
2017-04-10 10:27:01 +00:00
|
|
|
/**
|
|
|
|
* struct host1x_driver - host1x logical device driver
|
|
|
|
* @driver: core driver
|
|
|
|
* @subdevs: table of OF device IDs matching subdevices for this driver
|
|
|
|
* @list: list node for the driver
|
|
|
|
* @probe: called when the host1x logical device is probed
|
|
|
|
* @remove: called when the host1x logical device is removed
|
|
|
|
* @shutdown: called when the host1x logical device is shut down
|
|
|
|
*/
|
2013-10-14 12:43:22 +00:00
|
|
|
struct host1x_driver {
|
2014-12-18 14:29:14 +00:00
|
|
|
struct device_driver driver;
|
|
|
|
|
2013-10-14 12:43:22 +00:00
|
|
|
const struct of_device_id *subdevs;
|
|
|
|
struct list_head list;
|
|
|
|
|
|
|
|
int (*probe)(struct host1x_device *device);
|
|
|
|
int (*remove)(struct host1x_device *device);
|
2014-12-18 14:29:14 +00:00
|
|
|
void (*shutdown)(struct host1x_device *device);
|
2013-10-14 12:43:22 +00:00
|
|
|
};
|
|
|
|
|
2014-12-18 14:29:14 +00:00
|
|
|
static inline struct host1x_driver *
|
|
|
|
to_host1x_driver(struct device_driver *driver)
|
|
|
|
{
|
|
|
|
return container_of(driver, struct host1x_driver, driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
int host1x_driver_register_full(struct host1x_driver *driver,
|
|
|
|
struct module *owner);
|
2013-10-14 12:43:22 +00:00
|
|
|
void host1x_driver_unregister(struct host1x_driver *driver);
|
|
|
|
|
2014-12-18 14:29:14 +00:00
|
|
|
#define host1x_driver_register(driver) \
|
|
|
|
host1x_driver_register_full(driver, THIS_MODULE)
|
|
|
|
|
2013-10-14 12:43:22 +00:00
|
|
|
struct host1x_device {
|
|
|
|
struct host1x_driver *driver;
|
|
|
|
struct list_head list;
|
|
|
|
struct device dev;
|
|
|
|
|
|
|
|
struct mutex subdevs_lock;
|
|
|
|
struct list_head subdevs;
|
|
|
|
struct list_head active;
|
|
|
|
|
|
|
|
struct mutex clients_lock;
|
|
|
|
struct list_head clients;
|
2014-11-05 10:43:26 +00:00
|
|
|
|
2014-12-18 14:29:14 +00:00
|
|
|
bool registered;
|
2019-06-05 08:46:05 +00:00
|
|
|
|
|
|
|
struct device_dma_parameters dma_parms;
|
2013-10-14 12:43:22 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static inline struct host1x_device *to_host1x_device(struct device *dev)
|
|
|
|
{
|
|
|
|
return container_of(dev, struct host1x_device, dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
int host1x_device_init(struct host1x_device *device);
|
|
|
|
int host1x_device_exit(struct host1x_device *device);
|
|
|
|
|
2021-04-01 15:41:04 +00:00
|
|
|
void __host1x_client_init(struct host1x_client *client, struct lock_class_key *key);
|
|
|
|
void host1x_client_exit(struct host1x_client *client);
|
|
|
|
|
|
|
|
#define host1x_client_init(client) \
|
|
|
|
({ \
|
|
|
|
static struct lock_class_key __key; \
|
|
|
|
__host1x_client_init(client, &__key); \
|
|
|
|
})
|
|
|
|
|
|
|
|
int __host1x_client_register(struct host1x_client *client);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Note that this wrapper calls __host1x_client_init() for compatibility
|
|
|
|
* with existing callers. Callers that want to separately initialize and
|
|
|
|
* register a host1x client must first initialize using either of the
|
|
|
|
* __host1x_client_init() or host1x_client_init() functions and then use
|
|
|
|
* the low-level __host1x_client_register() function to avoid the client
|
|
|
|
* getting reinitialized.
|
|
|
|
*/
|
|
|
|
#define host1x_client_register(client) \
|
|
|
|
({ \
|
|
|
|
static struct lock_class_key __key; \
|
|
|
|
__host1x_client_init(client, &__key); \
|
|
|
|
__host1x_client_register(client); \
|
2021-03-29 13:38:27 +00:00
|
|
|
})
|
|
|
|
|
Merge DRM changes from upstream v6.3..v6.4
NOTE: This commit does not compile due to missing RHEL-specific fix-ups,
which are split out into separate Git commits following this one.
If git bisect selected this commit, run "git bisect skip" and try again.
Repeat this until it selects a commit which compiles.
This commit was generated using:
rhdrm-merge-drm v6.4 RHEL-1350
JIRA: https://issues.redhat.com/browse/RHEL-1350
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
drivers/gpu/drm/amd/display/dc/core/dc.c
drivers/gpu/drm/amd/display/dc/dc.h
drivers/gpu/drm/amd/display/dc/dc_dp_types.h
drivers/gpu/drm/amd/display/dc/dc_types.h
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
drivers/gpu/drm/amd/display/dc/inc/link.h
drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
drivers/gpu/drm/amd/display/dc/link/link_detection.c
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
drivers/gpu/drm/drm_displayid.c
drivers/gpu/drm/drm_fb_helper.c
drivers/gpu/drm/gma500/framebuffer.c
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
Conflict resolution:
diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0eb51c3a69a7,7acd73e5004f..11e99e8ca7ba
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@@ -350,35 -348,46 +348,75 @@@ static inline bool is_dc_timing_adjust_
return false;
}
+ static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
+ int planes_count)
+ {
+ int i, j;
+
+ for (i = 0, j = planes_count - 1; i < j; i++, j--)
+ swap(array_of_surface_update[i], array_of_surface_update[j]);
+ }
+
+ /**
+ * update_planes_and_stream_adapter() - Send planes to be updated in DC
+ *
+ * DC has a generic way to update planes and stream via
+ * dc_update_planes_and_stream function; however, DM might need some
+ * adjustments and preparation before calling it. This function is a wrapper
+ * for the dc_update_planes_and_stream that does any required configuration
+ * before passing control to DC.
+ */
+ static inline bool update_planes_and_stream_adapter(struct dc *dc,
+ int update_type,
+ int planes_count,
+ struct dc_stream_state *stream,
+ struct dc_stream_update *stream_update,
+ struct dc_surface_update *array_of_surface_update)
+ {
+ reverse_planes_order(array_of_surface_update, planes_count);
+
+ /*
+ * Previous frame finished and HW is ready for optimization.
+ */
+ if (update_type == UPDATE_TYPE_FAST)
+ dc_post_update_surfaces_to_stream(dc);
+
+ return dc_update_planes_and_stream(dc,
+ array_of_surface_update,
+ planes_count,
+ stream,
+ stream_update);
+ }
+
+/**
+ * update_planes_and_stream_adapter() - Send planes to be updated in DC
+ *
+ * DC has a generic way to update planes and stream via
+ * dc_update_planes_and_stream function; however, DM might need some
+ * adjustments and preparation before calling it. This function is a wrapper
+ * for the dc_update_planes_and_stream that does any required configuration
+ * before passing control to DC.
+ */
+static inline bool update_planes_and_stream_adapter(struct dc *dc,
+ int update_type,
+ int planes_count,
+ struct dc_stream_state *stream,
+ struct dc_stream_update *stream_update,
+ struct dc_surface_update *array_of_surface_update)
+{
+ /*
+ * Previous frame finished and HW is ready for optimization.
+ */
+ if (update_type == UPDATE_TYPE_FAST)
+ dc_post_update_surfaces_to_stream(dc);
+
+ return dc_update_planes_and_stream(dc,
+ array_of_surface_update,
+ planes_count,
+ stream,
+ stream_update);
+}
+
/**
* dm_pflip_high_irq() - Handle pageflip interrupt
* @interrupt_params: ignored
@@@ -7901,16 -7905,16 +7931,23 @@@ static void amdgpu_dm_commit_cursors(st
*/
for_each_old_plane_in_state(state, plane, old_plane_state, i)
if (plane->type == DRM_PLANE_TYPE_CURSOR)
- handle_cursor_update(plane, old_plane_state);
+ amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
+ }
+
+ static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
+ {
+ struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
+
+ return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
}
+static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
+{
+ struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
+
+ return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
+}
+
static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
struct dc_state *dc_state,
struct drm_device *dev,
diff --cc drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
index 862cb0f93b7d,18e098568cb4..3f047c985406
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
@@@ -142,49 -134,347 +134,391 @@@ void dc_restore_link_res_map(const stru
bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx)
{
- return link_update_dsc_config(pipe_ctx);
+ struct dc_link *link = pipe_ctx->stream->link;
+
+ return link->dc->link_srv->update_dsc_config(pipe_ctx);
+ }
+
+ bool dc_is_oem_i2c_device_present(
+ struct dc *dc,
+ size_t slave_address)
+ {
+ if (dc->res_pool->oem_device)
+ return dce_i2c_oem_device_present(
+ dc->res_pool,
+ dc->res_pool->oem_device,
+ slave_address);
+
+ return false;
+ }
+
+ bool dc_submit_i2c(
+ struct dc *dc,
+ uint32_t link_index,
+ struct i2c_command *cmd)
+ {
+
+ struct dc_link *link = dc->links[link_index];
+ struct ddc_service *ddc = link->ddc;
+
+ return dce_i2c_submit_command(
+ dc->res_pool,
+ ddc->ddc_pin,
+ cmd);
+ }
+
+ bool dc_submit_i2c_oem(
+ struct dc *dc,
+ struct i2c_command *cmd)
+ {
+ struct ddc_service *ddc = dc->res_pool->oem_device;
+
+ if (ddc)
+ return dce_i2c_submit_command(
+ dc->res_pool,
+ ddc->ddc_pin,
+ cmd);
+
+ return false;
+ }
+
+ void dc_link_dp_handle_automated_test(struct dc_link *link)
+ {
+ link->dc->link_srv->dp_handle_automated_test(link);
+ }
+
+ bool dc_link_dp_set_test_pattern(
+ struct dc_link *link,
+ enum dp_test_pattern test_pattern,
+ enum dp_test_pattern_color_space test_pattern_color_space,
+ const struct link_training_settings *p_link_settings,
+ const unsigned char *p_custom_pattern,
+ unsigned int cust_pattern_size)
+ {
+ return link->dc->link_srv->dp_set_test_pattern(link, test_pattern,
+ test_pattern_color_space, p_link_settings,
+ p_custom_pattern, cust_pattern_size);
+ }
+
+ void dc_link_set_drive_settings(struct dc *dc,
+ struct link_training_settings *lt_settings,
+ struct dc_link *link)
+ {
+ struct link_resource link_res;
+
+ dc->link_srv->get_cur_link_res(link, &link_res);
+ dc->link_srv->dp_set_drive_settings(link, &link_res, lt_settings);
+ }
+
+ void dc_link_set_preferred_link_settings(struct dc *dc,
+ struct dc_link_settings *link_setting,
+ struct dc_link *link)
+ {
+ dc->link_srv->dp_set_preferred_link_settings(dc, link_setting, link);
+ }
+
+ void dc_link_set_preferred_training_settings(struct dc *dc,
+ struct dc_link_settings *link_setting,
+ struct dc_link_training_overrides *lt_overrides,
+ struct dc_link *link,
+ bool skip_immediate_retrain)
+ {
+ dc->link_srv->dp_set_preferred_training_settings(dc, link_setting,
+ lt_overrides, link, skip_immediate_retrain);
+ }
+
+ bool dc_dp_trace_is_initialized(struct dc_link *link)
+ {
+ return link->dc->link_srv->dp_trace_is_initialized(link);
+ }
+
+ void dc_dp_trace_set_is_logged_flag(struct dc_link *link,
+ bool in_detection,
+ bool is_logged)
+ {
+ link->dc->link_srv->dp_trace_set_is_logged_flag(link, in_detection, is_logged);
+ }
+
+ bool dc_dp_trace_is_logged(struct dc_link *link, bool in_detection)
+ {
+ return link->dc->link_srv->dp_trace_is_logged(link, in_detection);
+ }
+
+ unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link,
+ bool in_detection)
+ {
+ return link->dc->link_srv->dp_trace_get_lt_end_timestamp(link, in_detection);
+ }
+
+ const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link,
+ bool in_detection)
+ {
+ return link->dc->link_srv->dp_trace_get_lt_counts(link, in_detection);
+ }
+
+ unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link)
+ {
+ return link->dc->link_srv->dp_trace_get_link_loss_count(link);
+ }
+
+ struct dc_sink *dc_link_add_remote_sink(
+ struct dc_link *link,
+ const uint8_t *edid,
+ int len,
+ struct dc_sink_init_data *init_data)
+ {
+ return link->dc->link_srv->add_remote_sink(link, edid, len, init_data);
+ }
+
+ void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
+ {
+ link->dc->link_srv->remove_remote_sink(link, sink);
+ }
+
+ int dc_link_aux_transfer_raw(struct ddc_service *ddc,
+ struct aux_payload *payload,
+ enum aux_return_code_type *operation_result)
+ {
+ const struct dc *dc = ddc->link->dc;
+
+ return dc->link_srv->aux_transfer_raw(
+ ddc, payload, operation_result);
+ }
+
+ uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw)
+ {
+ return dc->link_srv->bw_kbps_from_raw_frl_link_rate_data(bw);
+ }
+
+ bool dc_link_decide_edp_link_settings(struct dc_link *link,
+ struct dc_link_settings *link_setting, uint32_t req_bw)
+ {
+ return link->dc->link_srv->edp_decide_link_settings(link, link_setting, req_bw);
+ }
+
+
+ bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link,
+ struct dc_link_settings *max_link_enc_cap)
+ {
+ return link->dc->link_srv->dp_get_max_link_enc_cap(link, max_link_enc_cap);
+ }
+
+ enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(
+ const struct dc_link *link)
+ {
+ return link->dc->link_srv->mst_decide_link_encoding_format(link);
+ }
+
+ const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link)
+ {
+ return link->dc->link_srv->dp_get_verified_link_cap(link);
+ }
+
+ bool dc_link_is_dp_sink_present(struct dc_link *link)
+ {
+ return link->dc->link_srv->dp_is_sink_present(link);
+ }
+
+ bool dc_link_is_fec_supported(const struct dc_link *link)
+ {
+ return link->dc->link_srv->dp_is_fec_supported(link);
+ }
+
+ void dc_link_overwrite_extended_receiver_cap(
+ struct dc_link *link)
+ {
+ link->dc->link_srv->dp_overwrite_extended_receiver_cap(link);
+ }
+
+ bool dc_link_should_enable_fec(const struct dc_link *link)
+ {
+ return link->dc->link_srv->dp_should_enable_fec(link);
+ }
+
+ int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(
+ struct dc_link *link, int peak_bw)
+ {
+ return link->dc->link_srv->dpia_handle_usb4_bandwidth_allocation_for_link(link, peak_bw);
+ }
+
+ void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t result)
+ {
+ link->dc->link_srv->dpia_handle_bw_alloc_response(link, bw, result);
+ }
+
+ bool dc_link_check_link_loss_status(
+ struct dc_link *link,
+ union hpd_irq_data *hpd_irq_dpcd_data)
+ {
+ return link->dc->link_srv->dp_parse_link_loss_status(link, hpd_irq_dpcd_data);
+ }
+
+ bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link)
+ {
+ return link->dc->link_srv->dp_should_allow_hpd_rx_irq(link);
+ }
+
+ void dc_link_dp_handle_link_loss(struct dc_link *link)
+ {
+ link->dc->link_srv->dp_handle_link_loss(link);
+ }
+
+ enum dc_status dc_link_dp_read_hpd_rx_irq_data(
+ struct dc_link *link,
+ union hpd_irq_data *irq_data)
+ {
+ return link->dc->link_srv->dp_read_hpd_rx_irq_data(link, irq_data);
+ }
+
+ bool dc_link_handle_hpd_rx_irq(struct dc_link *link,
+ union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss,
+ bool defer_handling, bool *has_left_work)
+ {
+ return link->dc->link_srv->dp_handle_hpd_rx_irq(link, out_hpd_irq_dpcd_data,
+ out_link_loss, defer_handling, has_left_work);
+ }
+
+ void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on)
+ {
+ link->dc->link_srv->dpcd_write_rx_power_ctrl(link, on);
+ }
+
+ enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link,
+ struct dc_link_settings *link_setting)
+ {
+ return link->dc->link_srv->dp_decide_lttpr_mode(link, link_setting);
+ }
+
+ void dc_link_edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd)
+ {
+ link->dc->link_srv->edp_panel_backlight_power_on(link, wait_for_hpd);
+ }
+
+ int dc_link_get_backlight_level(const struct dc_link *link)
+ {
+ return link->dc->link_srv->edp_get_backlight_level(link);
+ }
+
+ bool dc_link_get_backlight_level_nits(struct dc_link *link,
+ uint32_t *backlight_millinits_avg,
+ uint32_t *backlight_millinits_peak)
+ {
+ return link->dc->link_srv->edp_get_backlight_level_nits(link,
+ backlight_millinits_avg,
+ backlight_millinits_peak);
+ }
+
+ bool dc_link_set_backlight_level(const struct dc_link *link,
+ uint32_t backlight_pwm_u16_16,
+ uint32_t frame_ramp)
+ {
+ return link->dc->link_srv->edp_set_backlight_level(link,
+ backlight_pwm_u16_16, frame_ramp);
+ }
+
+ bool dc_link_set_backlight_level_nits(struct dc_link *link,
+ bool isHDR,
+ uint32_t backlight_millinits,
+ uint32_t transition_time_in_ms)
+ {
+ return link->dc->link_srv->edp_set_backlight_level_nits(link, isHDR,
+ backlight_millinits, transition_time_in_ms);
+ }
+
+ int dc_link_get_target_backlight_pwm(const struct dc_link *link)
+ {
+ return link->dc->link_srv->edp_get_target_backlight_pwm(link);
+ }
+
+ bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
+ {
+ return link->dc->link_srv->edp_get_psr_state(link, state);
+ }
+
+ bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
+ bool wait, bool force_static, const unsigned int *power_opts)
+ {
+ return link->dc->link_srv->edp_set_psr_allow_active(link, allow_active, wait,
+ force_static, power_opts);
+ }
+
+ bool dc_link_setup_psr(struct dc_link *link,
+ const struct dc_stream_state *stream, struct psr_config *psr_config,
+ struct psr_context *psr_context)
+ {
+ return link->dc->link_srv->edp_setup_psr(link, stream, psr_config, psr_context);
+ }
+
+ bool dc_link_wait_for_t12(struct dc_link *link)
+ {
+ return link->dc->link_srv->edp_wait_for_t12(link);
+ }
+
+ bool dc_link_get_hpd_state(struct dc_link *link)
+ {
+ return link->dc->link_srv->get_hpd_state(link);
+ }
+
+ void dc_link_enable_hpd(const struct dc_link *link)
+ {
+ link->dc->link_srv->enable_hpd(link);
+ }
+
+ void dc_link_disable_hpd(const struct dc_link *link)
+ {
+ link->dc->link_srv->disable_hpd(link);
+ }
+
+ void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
+ {
+ link->dc->link_srv->enable_hpd_filter(link, enable);
+ }
+
+ bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, const unsigned int count)
+ {
+ return dc->link_srv->validate_dpia_bandwidth(streams, count);
}
+
+bool dc_is_oem_i2c_device_present(
+ struct dc *dc,
+ size_t slave_address)
+{
+ if (dc->res_pool->oem_device)
+ return dce_i2c_oem_device_present(
+ dc->res_pool,
+ dc->res_pool->oem_device,
+ slave_address);
+
+ return false;
+}
+
+bool dc_submit_i2c(
+ struct dc *dc,
+ uint32_t link_index,
+ struct i2c_command *cmd)
+{
+
+ struct dc_link *link = dc->links[link_index];
+ struct ddc_service *ddc = link->ddc;
+
+ return dce_i2c_submit_command(
+ dc->res_pool,
+ ddc->ddc_pin,
+ cmd);
+}
+
+bool dc_submit_i2c_oem(
+ struct dc *dc,
+ struct i2c_command *cmd)
+{
+ struct ddc_service *ddc = dc->res_pool->oem_device;
+
+ if (ddc)
+ return dce_i2c_submit_command(
+ dc->res_pool,
+ ddc->ddc_pin,
+ cmd);
+
+ return false;
+}
+
diff --cc drivers/gpu/drm/amd/display/dc/dc.h
index 9307442dc225,30f0ba05a6e6..49ac369cc926
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@@ -1663,39 -1664,36 +1664,83 @@@ bool dc_is_oem_i2c_device_present
/* return true if the connected receiver supports the hdcp version */
bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);
bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
- #endif
+
+ /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
+ *
+ * TODO - When defer_handling is true the function will have a different purpose.
+ * It no longer does complete hpd rx irq handling. We should create a separate
+ * interface specifically for this case.
+ *
+ * Return:
+ * true - Downstream port status changed. DM should call DC to do the
+ * detection.
+ * false - no change in Downstream port status. No further action required
+ * from DM.
+ */
+ bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
+ union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss,
+ bool defer_handling, bool *has_left_work);
+ /* handle DP specs define test automation sequence*/
+ void dc_link_dp_handle_automated_test(struct dc_link *link);
+
+ /* handle DP Link loss sequence and try to recover RX link loss with best
+ * effort
+ */
+ void dc_link_dp_handle_link_loss(struct dc_link *link);
+
+ /* Determine if hpd rx irq should be handled or ignored
+ * return true - hpd rx irq should be handled.
+ * return false - it is safe to ignore hpd rx irq event
+ */
+ bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link);
+
++/* Determine if link loss is indicated with a given hpd_irq_dpcd_data.
++ * @link - link the hpd irq data associated with
++ * @hpd_irq_dpcd_data - input hpd irq data
++ * return - true if hpd irq data indicates a link lost
++ */
++bool dc_link_check_link_loss_status(struct dc_link *link,
++ union hpd_irq_data *hpd_irq_dpcd_data);
++
++/* Read hpd rx irq data from a given link
++ * @link - link where the hpd irq data should be read from
++ * @irq_data - output hpd irq data
++ * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
++ * read has failed.
++ */
++enum dc_status dc_link_dp_read_hpd_rx_irq_data(
++ struct dc_link *link,
++ union hpd_irq_data *irq_data);
+
+/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
+ *
+ * TODO - When defer_handling is true the function will have a different purpose.
+ * It no longer does complete hpd rx irq handling. We should create a separate
+ * interface specifically for this case.
+ *
+ * Return:
+ * true - Downstream port status changed. DM should call DC to do the
+ * detection.
+ * false - no change in Downstream port status. No further action required
+ * from DM.
+ */
+bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
+ union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss,
+ bool defer_handling, bool *has_left_work);
+/* handle DP specs define test automation sequence*/
+void dc_link_dp_handle_automated_test(struct dc_link *link);
+
+/* handle DP Link loss sequence and try to recover RX link loss with best
+ * effort
+ */
+void dc_link_dp_handle_link_loss(struct dc_link *link);
+
+/* Determine if hpd rx irq should be handled or ignored
+ * return true - hpd rx irq should be handled.
+ * return false - it is safe to ignore hpd rx irq event
+ */
+bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link);
+
/* Determine if link loss is indicated with a given hpd_irq_dpcd_data.
* @link - link the hpd irq data associated with
* @hpd_irq_dpcd_data - input hpd irq data
diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 91b59d858108,eeca16faf31a..35333daf4cd9
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@@ -297,12 -309,33 +307,32 @@@ void dcn32_determine_det_override(struc
struct dc_plane_state *current_plane = NULL;
uint8_t stream_count = 0;
+ int phy_pix_clk_mult, lower_mode_stream_index;
+ int phy_pix_clk[MAX_PIPES] = {0};
+ bool use_new_det_override_algorithm = false;
+
for (i = 0; i < context->stream_count; i++) {
/* Don't count SubVP streams for DET allocation */
- if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM)
+ if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) {
+ phy_pix_clk[i] = context->streams[i]->phy_pix_clk;
stream_count++;
+ }
}
+ /* Check for special case with two displays, one with much higher pixel rate */
+ if (stream_count == 2) {
+ ASSERT((phy_pix_clk[0] > 0) && (phy_pix_clk[1] > 0));
+ if (phy_pix_clk[0] < phy_pix_clk[1]) {
+ lower_mode_stream_index = 0;
+ phy_pix_clk_mult = phy_pix_clk[1] / phy_pix_clk[0];
+ } else {
+ lower_mode_stream_index = 1;
+ phy_pix_clk_mult = phy_pix_clk[0] / phy_pix_clk[1];
+ }
+
+ if (phy_pix_clk_mult >= DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER)
+ use_new_det_override_algorithm = true;
+ }
+
if (stream_count > 0) {
stream_segments = 18 / stream_count;
for (i = 0; i < context->stream_count; i++) {
diff --cc drivers/gpu/drm/amd/display/dc/link/link_detection.c
index 8145d208512d,d471d58aba92..ee16d94b2b63
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@@ -1334,7 -1331,7 +1331,6 @@@ const struct dc_link_status *link_get_s
return &link->link_status;
}
--
static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
{
if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
diff --cc drivers/gpu/drm/bridge/tc358767.c
index 232e23a1bfcc,91f7cb56a654..d6349af4f1b6
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@@ -1896,12 -1896,12 +1896,12 @@@ static int tc_mipi_dsi_host_attach(stru
"failed to create dsi device\n");
tc->dsi = dsi;
-
dsi->lanes = dsi_lanes;
dsi->format = MIPI_DSI_FMT_RGB888;
- dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
- ret = mipi_dsi_attach(dsi);
+ ret = devm_mipi_dsi_attach(dev, dsi);
if (ret < 0) {
dev_err(dev, "failed to attach dsi to host: %d\n", ret);
return ret;
diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 8035e50f7422,3aeede6aee4d..ae367d473200
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@@ -2467,7 -2462,7 +2462,7 @@@ gen8_dispatch_bsd_engine(struct drm_i91
/* Check whether the file_priv has already selected one ring. */
if ((int)file_priv->bsd_engine < 0)
file_priv->bsd_engine =
- prandom_u32_max(num_vcs_engines(dev_priv));
- get_random_u32_below(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]);
++ prandom_u32_max(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]);
return file_priv->bsd_engine;
}
Commit list:
commit cbf143b282c64e59559cc8351c0b5b1ab4bbdcbe
commit d33a54e3991dfce88b4fc6d9c3360951c2c5660d
commit d703a0f45a70e6ed4749780ed5efb2d1ec042297
commit e566507bf2f460967f53030ef84b67ef26dcaf8e
commit 851a4a77a9f6441bd73625fe6dbc29c814ae681f
commit 18d2f6d956d0a39d5a27b0512aee17cb253f5788
commit 413ebc4803f025c64ec80de07c50e65e2f59ae89
commit 19ff997ffc43cb203fb7d6ac169b69e26c7dcbfb
commit 249a4f5e663ccd1c1b1d11db68020e488a020791
commit 357513233d6456c9f99e34794897efd4ae907e83
commit 6d8d5c6b643062a0dfc7632f7a73057e75fca057
commit 680d0c7960f12fc3852c70b2bab278cc5e70b88a
commit 7b775d36589390eaf19ceada78141c60ed1c7c84
commit f3783aa6b871ffece27388076d2c200a22bdb162
commit c886118bd8f574a635dda176b2460c03c28b1177
commit 0d6e08c72474043d7e686c32f25b735bfcdc9daa
commit 220b3376c0781ec46cf86e19b7460e7e1ccf913d
commit 6e52ced02392c760936159cc53da5669c94dd9a3
commit d374c047b38e9f1130308aae207dc44045cd5cac
commit 9b469093d321f23adf13d966797f55242278c3b5
commit 24efe424f096953d355cc366cdd471ba8cdaf035
commit 2b6f7e39ccae065abfbe3b6e562ec95ccad09f1e
commit 60bb4478f7de8ad45bc9464f94d766d8ec807606
commit fceeca7f3cf1c2b8628cd76c936b51271b793b1b
commit 28cbe92b59d7b8b1768f1900f677cf8567edd0bd
commit 1a45d6811c8790f4f9821038b243a71c9be1ebe2
commit d023d6f741c85bb00d2ca43d338327fbc150c113
commit c22cf04c6ab1d9ad5be2ec36e9822bc45526e8ca
commit 9d691c197631f152d7dc6788098f372b64d3bc43
commit d1702963ab145eff51c31e5fdc2867e9c5959ad5
commit 69ea87e1591a39dd53968f2f5d496f0f9499ad74
commit 3c4b33d0e67ddb900efa7a0eabd33a667c699ff9
commit 9c608cf39b96666ecbc163e3f6197f6d8ea78e56
commit 33d0c67dcbb045cbbbba9d41fa6e4b1f73bf3888
commit c76f67275f9c60d7ff53b6a90e90897c207d3d9c
commit 2324cdfffbaf0bc2404d919d9920b09148f8645f
commit 9dd56e979cb69f5cd904574c852b620777a2f69f
commit 16bede135fb1319c22dfa55b2de20f482fcc9cd9
commit 77d3b6130203299123d17df78b843f193c18b25f
commit 7f66476c930cdb5e0bc4dc563f241498a3791f99
commit 19d7dc6638a92535769b9ecc2b04a7f3afa0a7ed
commit 7fd7eacff0dec488071b5f1fedfcd382bf3ac074
commit 2a6d731a8f16192ece8e1649ca13e55d80561594
commit df5bf3b942a8d344bd9cbbe6ac31c9a2ea1557a4
commit c913cd5489930abbb557ef144a333846286754c3
commit 73a6c676542ac18d2556be80260bf554f1cef4ae
commit c580c2d27ac8754cc6f01da1d715b7272f5f9cbb
commit 43e6fad17a182de1825277d986a1e4309111e5b7
commit 9541fd164bddde24eb575c5744b6a31a6f62213e
commit 14f25bd0bb938af7359433db4ef9495aad4cf703
commit 4fae160fde76e9dc929ba57ec0efbbc1197daaf0
commit 1f16fdbb2a5a7504fcc4be057000e589cb427fbd
commit e4ef6503bd4c4ee6fbed2623c50a338dc93d5e9e
commit 23cc452e9b6186d6a8c1ddb380a0193652ea6579
commit 3965b8812e173c38b2fd1872dc3e08f436311575
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Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-01 05:07:01 +00:00
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void host1x_client_unregister(struct host1x_client *client);
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2013-10-14 12:43:22 +00:00
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2019-12-02 14:29:03 +00:00
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int host1x_client_suspend(struct host1x_client *client);
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int host1x_client_resume(struct host1x_client *client);
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2013-09-02 07:48:53 +00:00
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struct tegra_mipi_device;
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2020-07-15 04:20:51 +00:00
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struct tegra_mipi_device *tegra_mipi_request(struct device *device,
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struct device_node *np);
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2013-09-02 07:48:53 +00:00
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void tegra_mipi_free(struct tegra_mipi_device *device);
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2016-08-12 14:00:53 +00:00
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int tegra_mipi_enable(struct tegra_mipi_device *device);
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int tegra_mipi_disable(struct tegra_mipi_device *device);
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2020-08-12 00:27:19 +00:00
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int tegra_mipi_start_calibration(struct tegra_mipi_device *device);
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int tegra_mipi_finish_calibration(struct tegra_mipi_device *device);
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2013-09-02 07:48:53 +00:00
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2022-12-06 07:03:43 +00:00
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/* host1x memory contexts */
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struct host1x_memory_context {
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struct host1x *host;
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refcount_t ref;
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struct pid *owner;
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2025-01-27 18:16:06 +00:00
|
|
|
struct device_dma_parameters dma_parms;
|
2022-12-06 07:03:43 +00:00
|
|
|
struct device dev;
|
|
|
|
u64 dma_mask;
|
|
|
|
u32 stream_id;
|
|
|
|
};
|
|
|
|
|
|
|
|
#ifdef CONFIG_IOMMU_API
|
|
|
|
struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
|
2023-05-05 04:48:21 +00:00
|
|
|
struct device *dev,
|
2022-12-06 07:03:43 +00:00
|
|
|
struct pid *pid);
|
|
|
|
void host1x_memory_context_get(struct host1x_memory_context *cd);
|
|
|
|
void host1x_memory_context_put(struct host1x_memory_context *cd);
|
|
|
|
#else
|
|
|
|
static inline struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
|
2023-05-05 04:48:21 +00:00
|
|
|
struct device *dev,
|
2022-12-06 07:03:43 +00:00
|
|
|
struct pid *pid)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void host1x_memory_context_get(struct host1x_memory_context *cd)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void host1x_memory_context_put(struct host1x_memory_context *cd)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2013-03-22 14:34:03 +00:00
|
|
|
#endif
|