Charles Mirabile 55bb6ffeb7 perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus ...

JIRA: https://issues.redhat.com/browse/RHEL-176084

commit 49f2413f9b55dd975fb7d874c1fd35cf6a7335c6
Author: Besar Wicaksono <bwicaksono@nvidia.com>
Date: Mon, 8 Jun 2026 23:41:35 +0000

    The PMCCNTR_EL0 in NVIDIA Olympus CPU may increment while
    in WFI/WFE, which does not align with counting CPU_CYCLES
    on a programmable counter. Add a MIDR range entry and refuse
    PMCCNTR_EL0 for cycle events on affected parts so perf does
    not mix the two behaviors.

    Also keep PMCCNTR_EL0 unavailable to EL0 direct counter reads
    on affected CPUs. When userspace counter access is enabled,
    avoid setting PMUSERENR_EL0.CR for PMUs that must avoid
    PMCCNTR_EL0, while still allowing direct reads from programmable
    event counters. For 64-bit userspace CPU_CYCLES events on PMUs
    without native long event counters, reject the event if the only
    valid direct-read path would be PMCCNTR_EL0.

    Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
    Signed-off-by: Will Deacon <will@kernel.org>

Signed-off-by: Charles Mirabile <cmirabil@redhat.com>

2026-08-06 12:53:17 -04:00

..

arm_pmu.h

perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus

2026-08-06 12:53:17 -04:00

arm_pmuv3.h

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riscv_pmu.h

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