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Merge: perf: Add Intel DMR and NVL support
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-10/-/merge_requests/2891 JIRA: https://redhat.atlassian.net/browse/RHEL-95668 JIRA: https://redhat.atlassian.net/browse/RHEL-115120 JIRA: https://redhat.atlassian.net/browse/RHEL-115122 JIRA: https://redhat.atlassian.net/browse/RHEL-115124 JIRA: https://redhat.atlassian.net/browse/RHEL-117335 JIRA: https://redhat.atlassian.net/browse/RHEL-117337 JIRA: https://redhat.atlassian.net/browse/RHEL-120357 This MR brings PMU support for Intel Diamond Rapids and Nova Lake models. The features are split into multiple JIRA tickets, but make sense to merge together in one batch. This brings uncore, core and cstate support plus some fixes and extensions required by the mentioned platforms. Signed-off-by: Michael Petlan <mpetlan@redhat.com> Approved-by: Steve Best <sbest@redhat.com> Approved-by: tallison1 <tallison@redhat.com> Approved-by: ashelat <ashelat@redhat.com> Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com> Merged-by: CKI GitLab Kmaint Pipeline Bot <26919896-cki-kmaint-pipeline-bot@users.noreply.gitlab.com>
This commit is contained in:
CKI KWF Bot
@@ -0,0 +1,44 @@
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What: /sys/bus/event_source/devices/cpu.../rdpmc
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Date: November 2011
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KernelVersion: 3.10
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Contact: Linux kernel mailing list linux-kernel@vger.kernel.org
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Description: The /sys/bus/event_source/devices/cpu.../rdpmc attribute
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is used to show/manage if rdpmc instruction can be
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executed in user space. This attribute supports 3 numbers.
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- rdpmc = 0
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user space rdpmc is globally disabled for all PMU
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counters.
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- rdpmc = 1
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user space rdpmc is globally enabled only in event mmap
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ioctl called time window. If the mmap region is unmapped,
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user space rdpmc is disabled again.
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- rdpmc = 2
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user space rdpmc is globally enabled for all PMU
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counters.
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In the Intel platforms supporting counter level's user
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space rdpmc disable feature (CPUID.23H.EBX[2] = 1), the
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meaning of 3 numbers is extended to
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- rdpmc = 0
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global user space rdpmc and counter level's user space
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rdpmc of all counters are both disabled.
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- rdpmc = 1
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No changes on behavior of global user space rdpmc.
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counter level's rdpmc of system-wide events is disabled
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but counter level's rdpmc of non-system-wide events is
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enabled.
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- rdpmc = 2
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global user space rdpmc and counter level's user space
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rdpmc of all counters are both enabled unconditionally.
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The default value of rdpmc is 1.
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Please notice:
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- global user space rdpmc's behavior would change
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immediately along with the rdpmc value's change,
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but the behavior of counter level's user space rdpmc
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won't take effect immediately until the event is
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reactivated or recreated.
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- The rdpmc attribute is global, even for x86 hybrid
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platforms. For example, changing cpu_core/rdpmc will
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also change cpu_atom/rdpmc.
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+33
-8
@@ -1293,13 +1293,16 @@ int x86_perf_rdpmc_index(struct perf_event *event)
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return event->hw.event_base_rdpmc;
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}
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static inline int match_prev_assignment(struct hw_perf_event *hwc,
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static inline int match_prev_assignment(struct perf_event *event,
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struct cpu_hw_events *cpuc,
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int i)
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{
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struct hw_perf_event *hwc = &event->hw;
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return hwc->idx == cpuc->assign[i] &&
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hwc->last_cpu == smp_processor_id() &&
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hwc->last_tag == cpuc->tags[i];
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hwc->last_cpu == smp_processor_id() &&
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hwc->last_tag == cpuc->tags[i] &&
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!is_acr_event_group(event);
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}
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static void x86_pmu_start(struct perf_event *event, int flags);
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@@ -1345,7 +1348,7 @@ static void x86_pmu_enable(struct pmu *pmu)
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* - no other event has used the counter since
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*/
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if (hwc->idx == -1 ||
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match_prev_assignment(hwc, cpuc, i))
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match_prev_assignment(event, cpuc, i))
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continue;
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/*
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@@ -1366,7 +1369,7 @@ static void x86_pmu_enable(struct pmu *pmu)
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event = cpuc->event_list[i];
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hwc = &event->hw;
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if (!match_prev_assignment(hwc, cpuc, i))
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if (!match_prev_assignment(event, cpuc, i))
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x86_assign_hw_event(event, cpuc, i);
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else if (i < n_running)
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continue;
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@@ -2163,7 +2166,8 @@ static int __init init_hw_perf_events(void)
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pr_cont("%s PMU driver.\n", x86_pmu.name);
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x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
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/* enable userspace RDPMC usage by default */
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x86_pmu.attr_rdpmc = X86_USER_RDPMC_CONDITIONAL_ENABLE;
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for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
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quirk->func();
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@@ -2615,6 +2619,27 @@ static ssize_t get_attr_rdpmc(struct device *cdev,
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return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
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}
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/*
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* Behaviors of rdpmc value:
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* - rdpmc = 0
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* global user space rdpmc and counter level's user space rdpmc of all
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* counters are both disabled.
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* - rdpmc = 1
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* global user space rdpmc is enabled in mmap enabled time window and
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* counter level's user space rdpmc is enabled for only non system-wide
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* events. Counter level's user space rdpmc of system-wide events is
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* still disabled by default. This won't introduce counter data leak for
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* non system-wide events since their count data would be cleared when
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* context switches.
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* - rdpmc = 2
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* global user space rdpmc and counter level's user space rdpmc of all
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* counters are enabled unconditionally.
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*
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* Suppose the rdpmc value won't be changed frequently, don't dynamically
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* reschedule events to make the new rpdmc value take effect on active perf
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* events immediately, the new rdpmc value would only impact the new
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* activated perf events. This makes code simpler and cleaner.
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*/
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static ssize_t set_attr_rdpmc(struct device *cdev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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@@ -2643,12 +2668,12 @@ static ssize_t set_attr_rdpmc(struct device *cdev,
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*/
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if (val == 0)
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static_branch_inc(&rdpmc_never_available_key);
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else if (x86_pmu.attr_rdpmc == 0)
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else if (x86_pmu.attr_rdpmc == X86_USER_RDPMC_NEVER_ENABLE)
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static_branch_dec(&rdpmc_never_available_key);
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if (val == 2)
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static_branch_inc(&rdpmc_always_available_key);
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else if (x86_pmu.attr_rdpmc == 2)
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else if (x86_pmu.attr_rdpmc == X86_USER_RDPMC_ALWAYS_ENABLE)
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static_branch_dec(&rdpmc_always_available_key);
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on_each_cpu(cr4_update_pce, NULL, 1);
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+385
-29
@@ -231,6 +231,29 @@ static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
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EVENT_CONSTRAINT_END
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};
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static struct event_constraint intel_arw_event_constraints[] __read_mostly = {
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
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FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
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FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
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FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
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FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
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INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1),
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INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2),
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INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4),
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INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8),
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INTEL_UEVENT_CONSTRAINT(0x01d4, 0x1),
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INTEL_UEVENT_CONSTRAINT(0x02d4, 0x2),
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INTEL_UEVENT_CONSTRAINT(0x04d4, 0x4),
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INTEL_UEVENT_CONSTRAINT(0x08d4, 0x8),
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INTEL_UEVENT_CONSTRAINT(0x0175, 0x1),
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INTEL_UEVENT_CONSTRAINT(0x0275, 0x2),
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INTEL_UEVENT_CONSTRAINT(0x21d3, 0x1),
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INTEL_UEVENT_CONSTRAINT(0x22d3, 0x1),
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EVENT_CONSTRAINT_END
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};
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static struct event_constraint intel_skl_event_constraints[] = {
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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@@ -434,6 +457,62 @@ static struct extra_reg intel_lnc_extra_regs[] __read_mostly = {
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EVENT_EXTRA_END
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};
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static struct event_constraint intel_pnc_event_constraints[] = {
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
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FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
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METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
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METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
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METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
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METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
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METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
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METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
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METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
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METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
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INTEL_EVENT_CONSTRAINT(0x20, 0xf),
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INTEL_EVENT_CONSTRAINT(0x79, 0xf),
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INTEL_UEVENT_CONSTRAINT(0x0275, 0xf),
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INTEL_UEVENT_CONSTRAINT(0x0176, 0xf),
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INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
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INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
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INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfc),
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INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
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INTEL_EVENT_CONSTRAINT(0xd0, 0xf),
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INTEL_EVENT_CONSTRAINT(0xd1, 0xf),
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INTEL_EVENT_CONSTRAINT(0xd4, 0xf),
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INTEL_EVENT_CONSTRAINT(0xd6, 0xf),
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INTEL_EVENT_CONSTRAINT(0xdf, 0xf),
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INTEL_EVENT_CONSTRAINT(0xce, 0x1),
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INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
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INTEL_UEVENT_CONSTRAINT(0x0847, 0xf),
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INTEL_UEVENT_CONSTRAINT(0x0446, 0xf),
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INTEL_UEVENT_CONSTRAINT(0x0846, 0xf),
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INTEL_UEVENT_CONSTRAINT(0x0148, 0xf),
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EVENT_CONSTRAINT_END
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};
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static struct extra_reg intel_pnc_extra_regs[] __read_mostly = {
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/* must define OMR_X first, see intel_alt_er() */
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INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0),
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INTEL_UEVENT_EXTRA_REG(0x022a, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
|
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INTEL_UEVENT_EXTRA_REG(0x042a, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
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INTEL_UEVENT_EXTRA_REG(0x082a, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
|
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INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
|
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INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
|
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INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
|
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INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
|
||||
INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
|
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EVENT_EXTRA_END
|
||||
};
|
||||
|
||||
EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
|
||||
EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
|
||||
EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
|
||||
@@ -649,6 +728,102 @@ static __initconst const u64 glc_hw_cache_extra_regs
|
||||
},
|
||||
};
|
||||
|
||||
static __initconst const u64 pnc_hw_cache_event_ids
|
||||
[PERF_COUNT_HW_CACHE_MAX]
|
||||
[PERF_COUNT_HW_CACHE_OP_MAX]
|
||||
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
|
||||
{
|
||||
[ C(L1D ) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x81d0,
|
||||
[ C(RESULT_MISS) ] = 0xe124,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x82d0,
|
||||
},
|
||||
},
|
||||
[ C(L1I ) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_MISS) ] = 0xe424,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
},
|
||||
[ C(LL ) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x12a,
|
||||
[ C(RESULT_MISS) ] = 0x12a,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x12a,
|
||||
[ C(RESULT_MISS) ] = 0x12a,
|
||||
},
|
||||
},
|
||||
[ C(DTLB) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x81d0,
|
||||
[ C(RESULT_MISS) ] = 0xe12,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x82d0,
|
||||
[ C(RESULT_MISS) ] = 0xe13,
|
||||
},
|
||||
},
|
||||
[ C(ITLB) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = 0xe11,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
},
|
||||
[ C(BPU ) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x4c4,
|
||||
[ C(RESULT_MISS) ] = 0x4c5,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
},
|
||||
[ C(NODE) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static __initconst const u64 pnc_hw_cache_extra_regs
|
||||
[PERF_COUNT_HW_CACHE_MAX]
|
||||
[PERF_COUNT_HW_CACHE_OP_MAX]
|
||||
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
|
||||
{
|
||||
[ C(LL ) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x4000000000000001,
|
||||
[ C(RESULT_MISS) ] = 0xFFFFF000000001,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x4000000000000002,
|
||||
[ C(RESULT_MISS) ] = 0xFFFFF000000002,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* Notes on the events:
|
||||
* - data reads do not include code reads (comparable to earlier tables)
|
||||
@@ -2166,6 +2341,26 @@ static __initconst const u64 tnt_hw_cache_extra_regs
|
||||
},
|
||||
};
|
||||
|
||||
static __initconst const u64 arw_hw_cache_extra_regs
|
||||
[PERF_COUNT_HW_CACHE_MAX]
|
||||
[PERF_COUNT_HW_CACHE_OP_MAX]
|
||||
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
||||
[C(LL)] = {
|
||||
[C(OP_READ)] = {
|
||||
[C(RESULT_ACCESS)] = 0x4000000000000001,
|
||||
[C(RESULT_MISS)] = 0xFFFFF000000001,
|
||||
},
|
||||
[C(OP_WRITE)] = {
|
||||
[C(RESULT_ACCESS)] = 0x4000000000000002,
|
||||
[C(RESULT_MISS)] = 0xFFFFF000000002,
|
||||
},
|
||||
[C(OP_PREFETCH)] = {
|
||||
[C(RESULT_ACCESS)] = 0x0,
|
||||
[C(RESULT_MISS)] = 0x0,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
|
||||
EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
|
||||
EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
|
||||
@@ -2224,6 +2419,22 @@ static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
|
||||
EVENT_EXTRA_END
|
||||
};
|
||||
|
||||
static struct extra_reg intel_arw_extra_regs[] __read_mostly = {
|
||||
/* must define OMR_X first, see intel_alt_er() */
|
||||
INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0),
|
||||
INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),
|
||||
INTEL_UEVENT_EXTRA_REG(0x04b7, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),
|
||||
INTEL_UEVENT_EXTRA_REG(0x08b7, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),
|
||||
INTEL_UEVENT_EXTRA_REG(0x01d4, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0),
|
||||
INTEL_UEVENT_EXTRA_REG(0x02d4, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),
|
||||
INTEL_UEVENT_EXTRA_REG(0x04d4, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),
|
||||
INTEL_UEVENT_EXTRA_REG(0x08d4, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),
|
||||
INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
|
||||
INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
|
||||
INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
|
||||
EVENT_EXTRA_END
|
||||
};
|
||||
|
||||
EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_skt, "event=0x9c,umask=0x01");
|
||||
EVENT_ATTR_STR(topdown-retiring, td_retiring_skt, "event=0xc2,umask=0x02");
|
||||
EVENT_ATTR_STR(topdown-be-bound, td_be_bound_skt, "event=0xa4,umask=0x02");
|
||||
@@ -2906,16 +3117,18 @@ static void intel_pmu_enable_fixed(struct perf_event *event)
|
||||
intel_set_masks(event, idx);
|
||||
|
||||
/*
|
||||
* Enable IRQ generation (0x8), if not PEBS,
|
||||
* and enable ring-3 counting (0x2) and ring-0 counting (0x1)
|
||||
* if requested:
|
||||
* Enable IRQ generation (0x8), if not PEBS or self-reloaded
|
||||
* ACR event, and enable ring-3 counting (0x2) and ring-0
|
||||
* counting (0x1) if requested:
|
||||
*/
|
||||
if (!event->attr.precise_ip)
|
||||
if (!event->attr.precise_ip && !is_acr_self_reload_event(event))
|
||||
bits |= INTEL_FIXED_0_ENABLE_PMI;
|
||||
if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
|
||||
bits |= INTEL_FIXED_0_USER;
|
||||
if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
|
||||
bits |= INTEL_FIXED_0_KERNEL;
|
||||
if (hwc->config & ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE)
|
||||
bits |= INTEL_FIXED_0_RDPMC_USER_DISABLE;
|
||||
|
||||
/*
|
||||
* ANY bit is supported in v3 and up
|
||||
@@ -3051,6 +3264,27 @@ static void intel_pmu_enable_event_ext(struct perf_event *event)
|
||||
__intel_pmu_update_event_ext(hwc->idx, ext);
|
||||
}
|
||||
|
||||
static void intel_pmu_update_rdpmc_user_disable(struct perf_event *event)
|
||||
{
|
||||
if (!x86_pmu_has_rdpmc_user_disable(event->pmu))
|
||||
return;
|
||||
|
||||
/*
|
||||
* Counter scope's user-space rdpmc is disabled by default
|
||||
* except two cases.
|
||||
* a. rdpmc = 2 (user space rdpmc enabled unconditionally)
|
||||
* b. rdpmc = 1 and the event is not a system-wide event.
|
||||
* The count of non-system-wide events would be cleared when
|
||||
* context switches, so no count data is leaked.
|
||||
*/
|
||||
if (x86_pmu.attr_rdpmc == X86_USER_RDPMC_ALWAYS_ENABLE ||
|
||||
(x86_pmu.attr_rdpmc == X86_USER_RDPMC_CONDITIONAL_ENABLE &&
|
||||
event->ctx->task))
|
||||
event->hw.config &= ~ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
|
||||
else
|
||||
event->hw.config |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
|
||||
}
|
||||
|
||||
DEFINE_STATIC_CALL_NULL(intel_pmu_enable_event_ext, intel_pmu_enable_event_ext);
|
||||
|
||||
static void intel_pmu_enable_event(struct perf_event *event)
|
||||
@@ -3059,6 +3293,8 @@ static void intel_pmu_enable_event(struct perf_event *event)
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
int idx = hwc->idx;
|
||||
|
||||
intel_pmu_update_rdpmc_user_disable(event);
|
||||
|
||||
if (unlikely(event->attr.precise_ip))
|
||||
static_call(x86_pmu_pebs_enable)(event);
|
||||
|
||||
@@ -3069,6 +3305,15 @@ static void intel_pmu_enable_event(struct perf_event *event)
|
||||
intel_set_masks(event, idx);
|
||||
static_call_cond(intel_pmu_enable_acr_event)(event);
|
||||
static_call_cond(intel_pmu_enable_event_ext)(event);
|
||||
/*
|
||||
* For self-reloaded ACR event, don't enable PMI since
|
||||
* HW won't set overflow bit in GLOBAL_STATUS. Otherwise,
|
||||
* the PMI would be recognized as a suspicious NMI.
|
||||
*/
|
||||
if (is_acr_self_reload_event(event))
|
||||
hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
|
||||
else if (!event->attr.precise_ip)
|
||||
hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
|
||||
__x86_pmu_enable_event(hwc, enable_mask);
|
||||
break;
|
||||
case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
|
||||
@@ -3095,23 +3340,41 @@ static void intel_pmu_enable_event(struct perf_event *event)
|
||||
static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc)
|
||||
{
|
||||
struct perf_event *event, *leader;
|
||||
int i, j, idx;
|
||||
int i, j, k, bit, idx;
|
||||
|
||||
/*
|
||||
* FIXME: ACR mask parsing relies on cpuc->event_list[] (active events only).
|
||||
* Disabling an ACR event causes bit-shifting errors in the acr_mask of
|
||||
* remaining group members. As ACR sampling requires all events to be active,
|
||||
* this limitation is acceptable for now. Revisit if independent event toggling
|
||||
* is required.
|
||||
*/
|
||||
for (i = 0; i < cpuc->n_events; i++) {
|
||||
leader = cpuc->event_list[i];
|
||||
if (!is_acr_event_group(leader))
|
||||
continue;
|
||||
|
||||
/* The ACR events must be contiguous. */
|
||||
/* Find the last event of the ACR group. */
|
||||
for (j = i; j < cpuc->n_events; j++) {
|
||||
event = cpuc->event_list[j];
|
||||
if (event->group_leader != leader->group_leader)
|
||||
break;
|
||||
for_each_set_bit(idx, (unsigned long *)&event->attr.config2, X86_PMC_IDX_MAX) {
|
||||
if (i + idx >= cpuc->n_events ||
|
||||
!is_acr_event_group(cpuc->event_list[i + idx]))
|
||||
return;
|
||||
__set_bit(cpuc->assign[i + idx], (unsigned long *)&event->hw.config1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Translate the user-space ACR mask (attr.config2) into the physical
|
||||
* counter bitmask (hw.config1) for each ACR event in the group.
|
||||
* NOTE: ACR event contiguity is guaranteed by intel_pmu_hw_config().
|
||||
*/
|
||||
for (k = i; k < j; k++) {
|
||||
event = cpuc->event_list[k];
|
||||
event->hw.config1 = 0;
|
||||
for_each_set_bit(bit, (unsigned long *)&event->attr.config2, X86_PMC_IDX_MAX) {
|
||||
idx = i + bit;
|
||||
/* Event index of ACR group must locate in [i, j). */
|
||||
if (idx >= j || !is_acr_event_group(cpuc->event_list[idx]))
|
||||
continue;
|
||||
__set_bit(cpuc->assign[idx], (unsigned long *)&event->hw.config1);
|
||||
}
|
||||
}
|
||||
i = j - 1;
|
||||
@@ -3531,17 +3794,32 @@ static int intel_alt_er(struct cpu_hw_events *cpuc,
|
||||
struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
|
||||
int alt_idx = idx;
|
||||
|
||||
if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
|
||||
return idx;
|
||||
switch (idx) {
|
||||
case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1:
|
||||
if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
|
||||
return idx;
|
||||
if (++alt_idx > EXTRA_REG_RSP_1)
|
||||
alt_idx = EXTRA_REG_RSP_0;
|
||||
if (config & ~extra_regs[alt_idx].valid_mask)
|
||||
return idx;
|
||||
break;
|
||||
|
||||
if (idx == EXTRA_REG_RSP_0)
|
||||
alt_idx = EXTRA_REG_RSP_1;
|
||||
case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3:
|
||||
if (!(x86_pmu.flags & PMU_FL_HAS_OMR))
|
||||
return idx;
|
||||
if (++alt_idx > EXTRA_REG_OMR_3)
|
||||
alt_idx = EXTRA_REG_OMR_0;
|
||||
/*
|
||||
* Subtracting EXTRA_REG_OMR_0 ensures to get correct
|
||||
* OMR extra_reg entries which start from 0.
|
||||
*/
|
||||
if (config & ~extra_regs[alt_idx - EXTRA_REG_OMR_0].valid_mask)
|
||||
return idx;
|
||||
break;
|
||||
|
||||
if (idx == EXTRA_REG_RSP_1)
|
||||
alt_idx = EXTRA_REG_RSP_0;
|
||||
|
||||
if (config & ~extra_regs[alt_idx].valid_mask)
|
||||
return idx;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return alt_idx;
|
||||
}
|
||||
@@ -3549,16 +3827,26 @@ static int intel_alt_er(struct cpu_hw_events *cpuc,
|
||||
static void intel_fixup_er(struct perf_event *event, int idx)
|
||||
{
|
||||
struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
|
||||
event->hw.extra_reg.idx = idx;
|
||||
int er_idx;
|
||||
|
||||
if (idx == EXTRA_REG_RSP_0) {
|
||||
event->hw.extra_reg.idx = idx;
|
||||
switch (idx) {
|
||||
case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1:
|
||||
er_idx = idx - EXTRA_REG_RSP_0;
|
||||
event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
|
||||
event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event;
|
||||
event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
|
||||
} else if (idx == EXTRA_REG_RSP_1) {
|
||||
event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
|
||||
event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event;
|
||||
event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
|
||||
event->hw.config |= extra_regs[er_idx].event;
|
||||
event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0 + er_idx;
|
||||
break;
|
||||
|
||||
case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3:
|
||||
er_idx = idx - EXTRA_REG_OMR_0;
|
||||
event->hw.config &= ~ARCH_PERFMON_EVENTSEL_UMASK;
|
||||
event->hw.config |= 1ULL << (8 + er_idx);
|
||||
event->hw.extra_reg.reg = MSR_OMR_0 + er_idx;
|
||||
break;
|
||||
|
||||
default:
|
||||
pr_warn("The extra reg idx %d is not supported.\n", idx);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -5632,6 +5920,8 @@ static void update_pmu_cap(struct pmu *pmu)
|
||||
hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_UMASK2;
|
||||
if (ebx_0.split.eq)
|
||||
hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_EQ;
|
||||
if (ebx_0.split.rdpmc_user_disable)
|
||||
hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
|
||||
|
||||
if (eax_0.split.cntr_subleaf) {
|
||||
cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
|
||||
@@ -7210,6 +7500,21 @@ static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
|
||||
hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
|
||||
}
|
||||
|
||||
static __always_inline void intel_pmu_init_pnc(struct pmu *pmu)
|
||||
{
|
||||
intel_pmu_init_glc(pmu);
|
||||
x86_pmu.flags &= ~PMU_FL_HAS_RSP_1;
|
||||
x86_pmu.flags |= PMU_FL_HAS_OMR;
|
||||
memcpy(hybrid_var(pmu, hw_cache_event_ids),
|
||||
pnc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
|
||||
memcpy(hybrid_var(pmu, hw_cache_extra_regs),
|
||||
pnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
|
||||
hybrid(pmu, event_constraints) = intel_pnc_event_constraints;
|
||||
hybrid(pmu, pebs_constraints) = intel_pnc_pebs_event_constraints;
|
||||
hybrid(pmu, extra_regs) = intel_pnc_extra_regs;
|
||||
static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
|
||||
}
|
||||
|
||||
static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
|
||||
{
|
||||
intel_pmu_init_grt(pmu);
|
||||
@@ -7218,6 +7523,19 @@ static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
|
||||
static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
|
||||
}
|
||||
|
||||
static __always_inline void intel_pmu_init_arw(struct pmu *pmu)
|
||||
{
|
||||
intel_pmu_init_grt(pmu);
|
||||
x86_pmu.flags &= ~PMU_FL_HAS_RSP_1;
|
||||
x86_pmu.flags |= PMU_FL_HAS_OMR;
|
||||
memcpy(hybrid_var(pmu, hw_cache_extra_regs),
|
||||
arw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
|
||||
hybrid(pmu, event_constraints) = intel_arw_event_constraints;
|
||||
hybrid(pmu, pebs_constraints) = intel_arw_pebs_event_constraints;
|
||||
hybrid(pmu, extra_regs) = intel_arw_extra_regs;
|
||||
static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
|
||||
}
|
||||
|
||||
__init int intel_pmu_init(void)
|
||||
{
|
||||
struct attribute **extra_skl_attr = &empty_attrs;
|
||||
@@ -7870,9 +8188,21 @@ __init int intel_pmu_init(void)
|
||||
x86_pmu.extra_regs = intel_rwc_extra_regs;
|
||||
pr_cont("Granite Rapids events, ");
|
||||
name = "granite_rapids";
|
||||
goto glc_common;
|
||||
|
||||
case INTEL_DIAMONDRAPIDS_X:
|
||||
intel_pmu_init_pnc(NULL);
|
||||
x86_pmu.pebs_latency_data = pnc_latency_data;
|
||||
|
||||
pr_cont("Panthercove events, ");
|
||||
name = "panthercove";
|
||||
goto glc_base;
|
||||
|
||||
glc_common:
|
||||
intel_pmu_init_glc(NULL);
|
||||
intel_pmu_pebs_data_source_skl(true);
|
||||
|
||||
glc_base:
|
||||
x86_pmu.pebs_ept = 1;
|
||||
x86_pmu.hw_config = hsw_hw_config;
|
||||
x86_pmu.get_event_constraints = glc_get_event_constraints;
|
||||
@@ -7882,7 +8212,6 @@ __init int intel_pmu_init(void)
|
||||
mem_attr = glc_events_attrs;
|
||||
td_attr = glc_td_events_attrs;
|
||||
tsx_attr = glc_tsx_events_attrs;
|
||||
intel_pmu_pebs_data_source_skl(true);
|
||||
break;
|
||||
|
||||
case INTEL_ALDERLAKE:
|
||||
@@ -8046,6 +8375,33 @@ __init int intel_pmu_init(void)
|
||||
name = "arrowlake_h_hybrid";
|
||||
break;
|
||||
|
||||
case INTEL_NOVALAKE:
|
||||
case INTEL_NOVALAKE_L:
|
||||
pr_cont("Novalake Hybrid events, ");
|
||||
name = "novalake_hybrid";
|
||||
intel_pmu_init_hybrid(hybrid_big_small);
|
||||
|
||||
x86_pmu.pebs_latency_data = nvl_latency_data;
|
||||
x86_pmu.get_event_constraints = mtl_get_event_constraints;
|
||||
x86_pmu.hw_config = adl_hw_config;
|
||||
|
||||
td_attr = lnl_hybrid_events_attrs;
|
||||
mem_attr = mtl_hybrid_mem_attrs;
|
||||
tsx_attr = adl_hybrid_tsx_attrs;
|
||||
extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
|
||||
mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
|
||||
|
||||
/* Initialize big core specific PerfMon capabilities.*/
|
||||
pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
|
||||
intel_pmu_init_pnc(&pmu->pmu);
|
||||
|
||||
/* Initialize Atom core specific PerfMon capabilities.*/
|
||||
pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
|
||||
intel_pmu_init_arw(&pmu->pmu);
|
||||
|
||||
intel_pmu_pebs_data_source_lnl();
|
||||
break;
|
||||
|
||||
default:
|
||||
switch (x86_pmu.version) {
|
||||
case 1:
|
||||
|
||||
@@ -41,7 +41,7 @@
|
||||
* MSR_CORE_C1_RES: CORE C1 Residency Counter
|
||||
* perf code: 0x00
|
||||
* Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
|
||||
* MTL,SRF,GRR,ARL,LNL,PTL
|
||||
* MTL,SRF,GRR,ARL,LNL,PTL,WCL,NVL
|
||||
* Scope: Core (each processor core has a MSR)
|
||||
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
|
||||
* perf code: 0x01
|
||||
@@ -53,19 +53,20 @@
|
||||
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
|
||||
* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
|
||||
* TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
|
||||
* GRR,ARL,LNL,PTL
|
||||
* GRR,ARL,LNL,PTL,WCL,NVL
|
||||
* Scope: Core
|
||||
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
|
||||
* perf code: 0x03
|
||||
* Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
|
||||
* ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL,
|
||||
* PTL
|
||||
* PTL,WCL,NVL
|
||||
* Scope: Core
|
||||
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
|
||||
* perf code: 0x00
|
||||
* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
|
||||
* KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
|
||||
* RPL,SPR,MTL,ARL,LNL,SRF,PTL
|
||||
* RPL,SPR,MTL,ARL,LNL,SRF,PTL,WCL,
|
||||
* NVL
|
||||
* Scope: Package (physical package)
|
||||
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
|
||||
* perf code: 0x01
|
||||
@@ -78,7 +79,7 @@
|
||||
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
|
||||
* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
|
||||
* TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
|
||||
* ARL,LNL,PTL
|
||||
* ARL,LNL,PTL,WCL,NVL
|
||||
* Scope: Package (physical package)
|
||||
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
|
||||
* perf code: 0x03
|
||||
@@ -97,11 +98,12 @@
|
||||
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
|
||||
* perf code: 0x06
|
||||
* Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
|
||||
* TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL
|
||||
* TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL,
|
||||
* WCL,NVL
|
||||
* Scope: Package (physical package)
|
||||
* MSR_MODULE_C6_RES_MS: Module C6 Residency Counter.
|
||||
* perf code: 0x00
|
||||
* Available model: SRF,GRR
|
||||
* Available model: SRF,GRR,NVL
|
||||
* Scope: A cluster of cores shared L2 cache
|
||||
*
|
||||
*/
|
||||
@@ -526,6 +528,18 @@ static const struct cstate_model lnl_cstates __initconst = {
|
||||
BIT(PERF_CSTATE_PKG_C10_RES),
|
||||
};
|
||||
|
||||
static const struct cstate_model nvl_cstates __initconst = {
|
||||
.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
|
||||
BIT(PERF_CSTATE_CORE_C6_RES) |
|
||||
BIT(PERF_CSTATE_CORE_C7_RES),
|
||||
|
||||
.module_events = BIT(PERF_CSTATE_MODULE_C6_RES),
|
||||
|
||||
.pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
|
||||
BIT(PERF_CSTATE_PKG_C6_RES) |
|
||||
BIT(PERF_CSTATE_PKG_C10_RES),
|
||||
};
|
||||
|
||||
static const struct cstate_model slm_cstates __initconst = {
|
||||
.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
|
||||
BIT(PERF_CSTATE_CORE_C6_RES),
|
||||
@@ -637,6 +651,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
|
||||
X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &icx_cstates),
|
||||
X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &icx_cstates),
|
||||
X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, &icx_cstates),
|
||||
X86_MATCH_VFM(INTEL_DIAMONDRAPIDS_X, &srf_cstates),
|
||||
|
||||
X86_MATCH_VFM(INTEL_TIGERLAKE_L, &icl_cstates),
|
||||
X86_MATCH_VFM(INTEL_TIGERLAKE, &icl_cstates),
|
||||
@@ -653,6 +668,9 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
|
||||
X86_MATCH_VFM(INTEL_ARROWLAKE_U, &adl_cstates),
|
||||
X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_cstates),
|
||||
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &lnl_cstates),
|
||||
X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &lnl_cstates),
|
||||
X86_MATCH_VFM(INTEL_NOVALAKE, &nvl_cstates),
|
||||
X86_MATCH_VFM(INTEL_NOVALAKE_L, &nvl_cstates),
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
|
||||
|
||||
@@ -33,6 +33,17 @@ struct pebs_record_32 {
|
||||
|
||||
*/
|
||||
|
||||
union omr_encoding {
|
||||
struct {
|
||||
u8 omr_source : 4;
|
||||
u8 omr_remote : 1;
|
||||
u8 omr_hitm : 1;
|
||||
u8 omr_snoop : 1;
|
||||
u8 omr_promoted : 1;
|
||||
};
|
||||
u8 omr_full;
|
||||
};
|
||||
|
||||
union intel_x86_pebs_dse {
|
||||
u64 val;
|
||||
struct {
|
||||
@@ -72,6 +83,30 @@ union intel_x86_pebs_dse {
|
||||
unsigned int lnc_addr_blk:1;
|
||||
unsigned int ld_reserved6:18;
|
||||
};
|
||||
struct {
|
||||
unsigned int pnc_dse: 8;
|
||||
unsigned int pnc_l2_miss:1;
|
||||
unsigned int pnc_stlb_clean_hit:1;
|
||||
unsigned int pnc_stlb_any_hit:1;
|
||||
unsigned int pnc_stlb_miss:1;
|
||||
unsigned int pnc_locked:1;
|
||||
unsigned int pnc_data_blk:1;
|
||||
unsigned int pnc_addr_blk:1;
|
||||
unsigned int pnc_fb_full:1;
|
||||
unsigned int ld_reserved8:16;
|
||||
};
|
||||
struct {
|
||||
unsigned int arw_dse:8;
|
||||
unsigned int arw_l2_miss:1;
|
||||
unsigned int arw_xq_promotion:1;
|
||||
unsigned int arw_reissue:1;
|
||||
unsigned int arw_stlb_miss:1;
|
||||
unsigned int arw_locked:1;
|
||||
unsigned int arw_data_blk:1;
|
||||
unsigned int arw_addr_blk:1;
|
||||
unsigned int arw_fb_full:1;
|
||||
unsigned int ld_reserved9:16;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -227,6 +262,111 @@ void __init intel_pmu_pebs_data_source_lnl(void)
|
||||
__intel_pmu_pebs_data_source_cmt(data_source);
|
||||
}
|
||||
|
||||
/* Version for Panthercove and later */
|
||||
|
||||
/* L2 hit */
|
||||
#define PNC_PEBS_DATA_SOURCE_MAX 16
|
||||
static u64 pnc_pebs_l2_hit_data_source[PNC_PEBS_DATA_SOURCE_MAX] = {
|
||||
P(OP, LOAD) | P(LVL, NA) | LEVEL(NA) | P(SNOOP, NA), /* 0x00: non-cache access */
|
||||
OP_LH | LEVEL(L0) | P(SNOOP, NONE), /* 0x01: L0 hit */
|
||||
OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x02: L1 hit */
|
||||
OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x03: L1 Miss Handling Buffer hit */
|
||||
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x04: L2 Hit Clean */
|
||||
0, /* 0x05: Reserved */
|
||||
0, /* 0x06: Reserved */
|
||||
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT), /* 0x07: L2 Hit Snoop HIT */
|
||||
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM), /* 0x08: L2 Hit Snoop Hit Modified */
|
||||
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, MISS), /* 0x09: Prefetch Promotion */
|
||||
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, MISS), /* 0x0a: Cross Core Prefetch Promotion */
|
||||
0, /* 0x0b: Reserved */
|
||||
0, /* 0x0c: Reserved */
|
||||
0, /* 0x0d: Reserved */
|
||||
0, /* 0x0e: Reserved */
|
||||
OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
|
||||
};
|
||||
|
||||
/* Version for Arctic Wolf and later */
|
||||
|
||||
/* L2 hit */
|
||||
#define ARW_PEBS_DATA_SOURCE_MAX 16
|
||||
static u64 arw_pebs_l2_hit_data_source[ARW_PEBS_DATA_SOURCE_MAX] = {
|
||||
P(OP, LOAD) | P(LVL, NA) | LEVEL(NA) | P(SNOOP, NA), /* 0x00: non-cache access */
|
||||
OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 hit */
|
||||
OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: WCB Hit */
|
||||
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 Hit Clean */
|
||||
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT), /* 0x04: L2 Hit Snoop HIT */
|
||||
OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM), /* 0x05: L2 Hit Snoop Hit Modified */
|
||||
OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x06: uncached */
|
||||
0, /* 0x07: Reserved */
|
||||
0, /* 0x08: Reserved */
|
||||
0, /* 0x09: Reserved */
|
||||
0, /* 0x0a: Reserved */
|
||||
0, /* 0x0b: Reserved */
|
||||
0, /* 0x0c: Reserved */
|
||||
0, /* 0x0d: Reserved */
|
||||
0, /* 0x0e: Reserved */
|
||||
0, /* 0x0f: Reserved */
|
||||
};
|
||||
|
||||
/* L2 miss */
|
||||
#define OMR_DATA_SOURCE_MAX 16
|
||||
static u64 omr_data_source[OMR_DATA_SOURCE_MAX] = {
|
||||
P(OP, LOAD) | P(LVL, NA) | LEVEL(NA) | P(SNOOP, NA), /* 0x00: invalid */
|
||||
0, /* 0x01: Reserved */
|
||||
OP_LH | P(LVL, L3) | LEVEL(L3) | P(REGION, L_SHARE), /* 0x02: local CA shared cache */
|
||||
OP_LH | P(LVL, L3) | LEVEL(L3) | P(REGION, L_NON_SHARE),/* 0x03: local CA non-shared cache */
|
||||
OP_LH | P(LVL, L3) | LEVEL(L3) | P(REGION, O_IO), /* 0x04: other CA IO agent */
|
||||
OP_LH | P(LVL, L3) | LEVEL(L3) | P(REGION, O_SHARE), /* 0x05: other CA shared cache */
|
||||
OP_LH | P(LVL, L3) | LEVEL(L3) | P(REGION, O_NON_SHARE),/* 0x06: other CA non-shared cache */
|
||||
OP_LH | LEVEL(RAM) | P(REGION, MMIO), /* 0x07: MMIO */
|
||||
OP_LH | LEVEL(RAM) | P(REGION, MEM0), /* 0x08: Memory region 0 */
|
||||
OP_LH | LEVEL(RAM) | P(REGION, MEM1), /* 0x09: Memory region 1 */
|
||||
OP_LH | LEVEL(RAM) | P(REGION, MEM2), /* 0x0a: Memory region 2 */
|
||||
OP_LH | LEVEL(RAM) | P(REGION, MEM3), /* 0x0b: Memory region 3 */
|
||||
OP_LH | LEVEL(RAM) | P(REGION, MEM4), /* 0x0c: Memory region 4 */
|
||||
OP_LH | LEVEL(RAM) | P(REGION, MEM5), /* 0x0d: Memory region 5 */
|
||||
OP_LH | LEVEL(RAM) | P(REGION, MEM6), /* 0x0e: Memory region 6 */
|
||||
OP_LH | LEVEL(RAM) | P(REGION, MEM7), /* 0x0f: Memory region 7 */
|
||||
};
|
||||
|
||||
static u64 parse_omr_data_source(u8 dse)
|
||||
{
|
||||
union omr_encoding omr;
|
||||
u64 val = 0;
|
||||
|
||||
omr.omr_full = dse;
|
||||
val = omr_data_source[omr.omr_source];
|
||||
if (omr.omr_source > 0x1 && omr.omr_source < 0x7)
|
||||
val |= omr.omr_remote ? P(LVL, REM_CCE1) : 0;
|
||||
else if (omr.omr_source > 0x7)
|
||||
val |= omr.omr_remote ? P(LVL, REM_RAM1) : P(LVL, LOC_RAM);
|
||||
|
||||
if (omr.omr_remote)
|
||||
val |= REM;
|
||||
|
||||
if (omr.omr_source == 0x2) {
|
||||
u8 snoop = omr.omr_snoop | (omr.omr_promoted << 1);
|
||||
|
||||
if (omr.omr_hitm)
|
||||
val |= P(SNOOP, HITM);
|
||||
else if (snoop == 0x0)
|
||||
val |= P(SNOOP, NA);
|
||||
else if (snoop == 0x1)
|
||||
val |= P(SNOOP, MISS);
|
||||
else if (snoop == 0x2)
|
||||
val |= P(SNOOP, HIT);
|
||||
else if (snoop == 0x3)
|
||||
val |= P(SNOOP, NONE);
|
||||
} else if (omr.omr_source > 0x2 && omr.omr_source < 0x7) {
|
||||
val |= omr.omr_hitm ? P(SNOOP, HITM) : P(SNOOP, HIT);
|
||||
val |= omr.omr_snoop ? P(SNOOPX, FWD) : 0;
|
||||
} else {
|
||||
val |= P(SNOOP, NONE);
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static u64 precise_store_data(u64 status)
|
||||
{
|
||||
union intel_x86_pebs_dse dse;
|
||||
@@ -355,6 +495,44 @@ u64 cmt_latency_data(struct perf_event *event, u64 status)
|
||||
dse.mtl_fwd_blk);
|
||||
}
|
||||
|
||||
static u64 arw_latency_data(struct perf_event *event, u64 status)
|
||||
{
|
||||
union intel_x86_pebs_dse dse;
|
||||
union perf_mem_data_src src;
|
||||
u64 val;
|
||||
|
||||
dse.val = status;
|
||||
|
||||
if (!dse.arw_l2_miss)
|
||||
val = arw_pebs_l2_hit_data_source[dse.arw_dse & 0xf];
|
||||
else
|
||||
val = parse_omr_data_source(dse.arw_dse);
|
||||
|
||||
if (!val)
|
||||
val = P(OP, LOAD) | LEVEL(NA) | P(SNOOP, NA);
|
||||
|
||||
if (dse.arw_stlb_miss)
|
||||
val |= P(TLB, MISS) | P(TLB, L2);
|
||||
else
|
||||
val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
|
||||
|
||||
if (dse.arw_locked)
|
||||
val |= P(LOCK, LOCKED);
|
||||
|
||||
if (dse.arw_data_blk)
|
||||
val |= P(BLK, DATA);
|
||||
if (dse.arw_addr_blk)
|
||||
val |= P(BLK, ADDR);
|
||||
if (!dse.arw_data_blk && !dse.arw_addr_blk)
|
||||
val |= P(BLK, NA);
|
||||
|
||||
src.val = val;
|
||||
if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
|
||||
src.mem_op = P(OP, STORE);
|
||||
|
||||
return src.val;
|
||||
}
|
||||
|
||||
static u64 lnc_latency_data(struct perf_event *event, u64 status)
|
||||
{
|
||||
union intel_x86_pebs_dse dse;
|
||||
@@ -410,6 +588,54 @@ u64 arl_h_latency_data(struct perf_event *event, u64 status)
|
||||
return lnl_latency_data(event, status);
|
||||
}
|
||||
|
||||
u64 pnc_latency_data(struct perf_event *event, u64 status)
|
||||
{
|
||||
union intel_x86_pebs_dse dse;
|
||||
union perf_mem_data_src src;
|
||||
u64 val;
|
||||
|
||||
dse.val = status;
|
||||
|
||||
if (!dse.pnc_l2_miss)
|
||||
val = pnc_pebs_l2_hit_data_source[dse.pnc_dse & 0xf];
|
||||
else
|
||||
val = parse_omr_data_source(dse.pnc_dse);
|
||||
|
||||
if (!val)
|
||||
val = P(OP, LOAD) | LEVEL(NA) | P(SNOOP, NA);
|
||||
|
||||
if (dse.pnc_stlb_miss)
|
||||
val |= P(TLB, MISS) | P(TLB, L2);
|
||||
else
|
||||
val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
|
||||
|
||||
if (dse.pnc_locked)
|
||||
val |= P(LOCK, LOCKED);
|
||||
|
||||
if (dse.pnc_data_blk)
|
||||
val |= P(BLK, DATA);
|
||||
if (dse.pnc_addr_blk)
|
||||
val |= P(BLK, ADDR);
|
||||
if (!dse.pnc_data_blk && !dse.pnc_addr_blk)
|
||||
val |= P(BLK, NA);
|
||||
|
||||
src.val = val;
|
||||
if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
|
||||
src.mem_op = P(OP, STORE);
|
||||
|
||||
return src.val;
|
||||
}
|
||||
|
||||
u64 nvl_latency_data(struct perf_event *event, u64 status)
|
||||
{
|
||||
struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
|
||||
|
||||
if (pmu->pmu_type == hybrid_small)
|
||||
return arw_latency_data(event, status);
|
||||
|
||||
return pnc_latency_data(event, status);
|
||||
}
|
||||
|
||||
static u64 load_latency_data(struct perf_event *event, u64 status)
|
||||
{
|
||||
union intel_x86_pebs_dse dse;
|
||||
@@ -1069,6 +1295,17 @@ struct event_constraint intel_grt_pebs_event_constraints[] = {
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
struct event_constraint intel_arw_pebs_event_constraints[] = {
|
||||
/* Allow all events as PEBS with no flags */
|
||||
INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff),
|
||||
INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff),
|
||||
INTEL_FLAGS_UEVENT_CONSTRAINT(0x01d4, 0x1),
|
||||
INTEL_FLAGS_UEVENT_CONSTRAINT(0x02d4, 0x2),
|
||||
INTEL_FLAGS_UEVENT_CONSTRAINT(0x04d4, 0x4),
|
||||
INTEL_FLAGS_UEVENT_CONSTRAINT(0x08d4, 0x8),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
struct event_constraint intel_nehalem_pebs_event_constraints[] = {
|
||||
INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
|
||||
INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
|
||||
@@ -1284,6 +1521,33 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = {
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
struct event_constraint intel_pnc_pebs_event_constraints[] = {
|
||||
INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
|
||||
INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
|
||||
|
||||
INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0xfc),
|
||||
INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
|
||||
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
|
||||
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
|
||||
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
|
||||
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
|
||||
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
|
||||
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
|
||||
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
|
||||
|
||||
INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
|
||||
|
||||
INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
|
||||
INTEL_FLAGS_EVENT_CONSTRAINT(0xd6, 0xf),
|
||||
|
||||
/*
|
||||
* Everything else is handled by PMU_FL_PEBS_ALL, because we
|
||||
* need the full constraints from the main table.
|
||||
*/
|
||||
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
struct event_constraint *intel_pebs_constraints(struct perf_event *event)
|
||||
{
|
||||
struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints);
|
||||
|
||||
@@ -242,7 +242,7 @@ static __init void p6_pmu_rdpmc_quirk(void)
|
||||
*/
|
||||
pr_warn("Userspace RDPMC support disabled due to a CPU erratum\n");
|
||||
x86_pmu.attr_rdpmc_broken = 1;
|
||||
x86_pmu.attr_rdpmc = 0;
|
||||
x86_pmu.attr_rdpmc = X86_USER_RDPMC_NEVER_ENABLE;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -66,6 +66,7 @@ int uncore_die_to_segment(int die)
|
||||
return bus ? pci_domain_nr(bus) : -EINVAL;
|
||||
}
|
||||
|
||||
/* Note: This API can only be used when NUMA information is available. */
|
||||
int uncore_device_to_die(struct pci_dev *dev)
|
||||
{
|
||||
int node = pcibus_to_node(dev->bus);
|
||||
@@ -435,7 +436,7 @@ uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *eve
|
||||
|
||||
if (type->constraints) {
|
||||
for_each_event_constraint(c, type->constraints) {
|
||||
if ((event->hw.config & c->cmask) == c->code)
|
||||
if (constraint_match(c, event->hw.config))
|
||||
return c;
|
||||
}
|
||||
}
|
||||
@@ -1696,152 +1697,181 @@ err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct intel_uncore_init_fun {
|
||||
void (*cpu_init)(void);
|
||||
int (*pci_init)(void);
|
||||
void (*mmio_init)(void);
|
||||
/* Discovery table is required */
|
||||
bool use_discovery;
|
||||
/* The units in the discovery table should be ignored. */
|
||||
int *uncore_units_ignore;
|
||||
};
|
||||
static int uncore_mmio_global_init(u64 ctl)
|
||||
{
|
||||
void __iomem *io_addr;
|
||||
|
||||
static const struct intel_uncore_init_fun nhm_uncore_init __initconst = {
|
||||
io_addr = ioremap(ctl, sizeof(ctl));
|
||||
if (!io_addr)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Clear freeze bit (0) to enable all counters. */
|
||||
writel(0, io_addr);
|
||||
|
||||
iounmap(io_addr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct uncore_plat_init nhm_uncore_init __initconst = {
|
||||
.cpu_init = nhm_uncore_cpu_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun snb_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init snb_uncore_init __initconst = {
|
||||
.cpu_init = snb_uncore_cpu_init,
|
||||
.pci_init = snb_uncore_pci_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun ivb_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init ivb_uncore_init __initconst = {
|
||||
.cpu_init = snb_uncore_cpu_init,
|
||||
.pci_init = ivb_uncore_pci_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun hsw_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init hsw_uncore_init __initconst = {
|
||||
.cpu_init = snb_uncore_cpu_init,
|
||||
.pci_init = hsw_uncore_pci_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun bdw_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init bdw_uncore_init __initconst = {
|
||||
.cpu_init = snb_uncore_cpu_init,
|
||||
.pci_init = bdw_uncore_pci_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun snbep_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init snbep_uncore_init __initconst = {
|
||||
.cpu_init = snbep_uncore_cpu_init,
|
||||
.pci_init = snbep_uncore_pci_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun nhmex_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init nhmex_uncore_init __initconst = {
|
||||
.cpu_init = nhmex_uncore_cpu_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun ivbep_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init ivbep_uncore_init __initconst = {
|
||||
.cpu_init = ivbep_uncore_cpu_init,
|
||||
.pci_init = ivbep_uncore_pci_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun hswep_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init hswep_uncore_init __initconst = {
|
||||
.cpu_init = hswep_uncore_cpu_init,
|
||||
.pci_init = hswep_uncore_pci_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun bdx_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init bdx_uncore_init __initconst = {
|
||||
.cpu_init = bdx_uncore_cpu_init,
|
||||
.pci_init = bdx_uncore_pci_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun knl_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init knl_uncore_init __initconst = {
|
||||
.cpu_init = knl_uncore_cpu_init,
|
||||
.pci_init = knl_uncore_pci_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun skl_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init skl_uncore_init __initconst = {
|
||||
.cpu_init = skl_uncore_cpu_init,
|
||||
.pci_init = skl_uncore_pci_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun skx_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init skx_uncore_init __initconst = {
|
||||
.cpu_init = skx_uncore_cpu_init,
|
||||
.pci_init = skx_uncore_pci_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun icl_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init icl_uncore_init __initconst = {
|
||||
.cpu_init = icl_uncore_cpu_init,
|
||||
.pci_init = skl_uncore_pci_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun tgl_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init tgl_uncore_init __initconst = {
|
||||
.cpu_init = tgl_uncore_cpu_init,
|
||||
.mmio_init = tgl_uncore_mmio_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun tgl_l_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init tgl_l_uncore_init __initconst = {
|
||||
.cpu_init = tgl_uncore_cpu_init,
|
||||
.mmio_init = tgl_l_uncore_mmio_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun rkl_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init rkl_uncore_init __initconst = {
|
||||
.cpu_init = tgl_uncore_cpu_init,
|
||||
.pci_init = skl_uncore_pci_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun adl_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init adl_uncore_init __initconst = {
|
||||
.cpu_init = adl_uncore_cpu_init,
|
||||
.mmio_init = adl_uncore_mmio_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun mtl_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init mtl_uncore_init __initconst = {
|
||||
.cpu_init = mtl_uncore_cpu_init,
|
||||
.mmio_init = adl_uncore_mmio_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun lnl_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init lnl_uncore_init __initconst = {
|
||||
.cpu_init = lnl_uncore_cpu_init,
|
||||
.mmio_init = lnl_uncore_mmio_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun ptl_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init ptl_uncore_init __initconst = {
|
||||
.cpu_init = ptl_uncore_cpu_init,
|
||||
.mmio_init = ptl_uncore_mmio_init,
|
||||
.use_discovery = true,
|
||||
.domain[0].discovery_base = UNCORE_DISCOVERY_MSR,
|
||||
.domain[0].global_init = uncore_mmio_global_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun icx_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init nvl_uncore_init __initconst = {
|
||||
.cpu_init = nvl_uncore_cpu_init,
|
||||
.mmio_init = ptl_uncore_mmio_init,
|
||||
.domain[0].discovery_base = PACKAGE_UNCORE_DISCOVERY_MSR,
|
||||
.domain[0].global_init = uncore_mmio_global_init,
|
||||
};
|
||||
|
||||
static const struct uncore_plat_init icx_uncore_init __initconst = {
|
||||
.cpu_init = icx_uncore_cpu_init,
|
||||
.pci_init = icx_uncore_pci_init,
|
||||
.mmio_init = icx_uncore_mmio_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun snr_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init snr_uncore_init __initconst = {
|
||||
.cpu_init = snr_uncore_cpu_init,
|
||||
.pci_init = snr_uncore_pci_init,
|
||||
.mmio_init = snr_uncore_mmio_init,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun spr_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init spr_uncore_init __initconst = {
|
||||
.cpu_init = spr_uncore_cpu_init,
|
||||
.pci_init = spr_uncore_pci_init,
|
||||
.mmio_init = spr_uncore_mmio_init,
|
||||
.use_discovery = true,
|
||||
.uncore_units_ignore = spr_uncore_units_ignore,
|
||||
.domain[0].base_is_pci = true,
|
||||
.domain[0].discovery_base = UNCORE_DISCOVERY_TABLE_DEVICE,
|
||||
.domain[0].units_ignore = spr_uncore_units_ignore,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun gnr_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init gnr_uncore_init __initconst = {
|
||||
.cpu_init = gnr_uncore_cpu_init,
|
||||
.pci_init = gnr_uncore_pci_init,
|
||||
.mmio_init = gnr_uncore_mmio_init,
|
||||
.use_discovery = true,
|
||||
.uncore_units_ignore = gnr_uncore_units_ignore,
|
||||
.domain[0].base_is_pci = true,
|
||||
.domain[0].discovery_base = UNCORE_DISCOVERY_TABLE_DEVICE,
|
||||
.domain[0].units_ignore = gnr_uncore_units_ignore,
|
||||
};
|
||||
|
||||
static const struct intel_uncore_init_fun generic_uncore_init __initconst = {
|
||||
static const struct uncore_plat_init dmr_uncore_init __initconst = {
|
||||
.pci_init = dmr_uncore_pci_init,
|
||||
.mmio_init = dmr_uncore_mmio_init,
|
||||
.domain[0].base_is_pci = true,
|
||||
.domain[0].discovery_base = DMR_UNCORE_DISCOVERY_TABLE_DEVICE,
|
||||
.domain[0].units_ignore = dmr_uncore_imh_units_ignore,
|
||||
.domain[1].discovery_base = CBB_UNCORE_DISCOVERY_MSR,
|
||||
.domain[1].units_ignore = dmr_uncore_cbb_units_ignore,
|
||||
.domain[1].global_init = uncore_mmio_global_init,
|
||||
};
|
||||
|
||||
static const struct uncore_plat_init generic_uncore_init __initconst = {
|
||||
.cpu_init = intel_uncore_generic_uncore_cpu_init,
|
||||
.pci_init = intel_uncore_generic_uncore_pci_init,
|
||||
.mmio_init = intel_uncore_generic_uncore_mmio_init,
|
||||
.domain[0].base_is_pci = true,
|
||||
.domain[0].discovery_base = PCI_ANY_ID,
|
||||
.domain[1].discovery_base = UNCORE_DISCOVERY_MSR,
|
||||
};
|
||||
|
||||
static const struct x86_cpu_id intel_uncore_match[] __initconst = {
|
||||
@@ -1893,6 +1923,8 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
|
||||
X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_uncore_init),
|
||||
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &ptl_uncore_init),
|
||||
X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &ptl_uncore_init),
|
||||
X86_MATCH_VFM(INTEL_NOVALAKE, &nvl_uncore_init),
|
||||
X86_MATCH_VFM(INTEL_NOVALAKE_L, &nvl_uncore_init),
|
||||
X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &spr_uncore_init),
|
||||
X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &spr_uncore_init),
|
||||
X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &gnr_uncore_init),
|
||||
@@ -1902,14 +1934,25 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
|
||||
X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, &gnr_uncore_init),
|
||||
X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, &gnr_uncore_init),
|
||||
X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X, &gnr_uncore_init),
|
||||
X86_MATCH_VFM(INTEL_DIAMONDRAPIDS_X, &dmr_uncore_init),
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, intel_uncore_match);
|
||||
|
||||
static bool uncore_use_discovery(struct uncore_plat_init *config)
|
||||
{
|
||||
for (int i = 0; i < UNCORE_DISCOVERY_DOMAINS; i++) {
|
||||
if (config->domain[i].discovery_base)
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int __init intel_uncore_init(void)
|
||||
{
|
||||
const struct x86_cpu_id *id;
|
||||
struct intel_uncore_init_fun *uncore_init;
|
||||
struct uncore_plat_init *uncore_init;
|
||||
int pret = 0, cret = 0, mret = 0, ret;
|
||||
|
||||
if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
|
||||
@@ -1920,16 +1963,15 @@ static int __init intel_uncore_init(void)
|
||||
|
||||
id = x86_match_cpu(intel_uncore_match);
|
||||
if (!id) {
|
||||
if (!uncore_no_discover && intel_uncore_has_discovery_tables(NULL))
|
||||
uncore_init = (struct intel_uncore_init_fun *)&generic_uncore_init;
|
||||
else
|
||||
uncore_init = (struct uncore_plat_init *)&generic_uncore_init;
|
||||
if (uncore_no_discover || !uncore_discovery(uncore_init))
|
||||
return -ENODEV;
|
||||
} else {
|
||||
uncore_init = (struct intel_uncore_init_fun *)id->driver_data;
|
||||
if (uncore_no_discover && uncore_init->use_discovery)
|
||||
uncore_init = (struct uncore_plat_init *)id->driver_data;
|
||||
if (uncore_no_discover && uncore_use_discovery(uncore_init))
|
||||
return -ENODEV;
|
||||
if (uncore_init->use_discovery &&
|
||||
!intel_uncore_has_discovery_tables(uncore_init->uncore_units_ignore))
|
||||
if (uncore_use_discovery(uncore_init) &&
|
||||
!uncore_discovery(uncore_init))
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
|
||||
@@ -33,6 +33,8 @@
|
||||
#define UNCORE_EXTRA_PCI_DEV_MAX 4
|
||||
|
||||
#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
|
||||
#define UNCORE_EVENT_CONSTRAINT_RANGE(c, e, n) \
|
||||
EVENT_CONSTRAINT_RANGE(c, e, n, 0xff)
|
||||
|
||||
#define UNCORE_IGNORE_END -1
|
||||
|
||||
@@ -47,6 +49,25 @@ struct uncore_event_desc;
|
||||
struct freerunning_counters;
|
||||
struct intel_uncore_topology;
|
||||
|
||||
struct uncore_discovery_domain {
|
||||
/* MSR address or PCI device used as the discovery base */
|
||||
u32 discovery_base;
|
||||
bool base_is_pci;
|
||||
int (*global_init)(u64 ctl);
|
||||
|
||||
/* The units in the discovery table should be ignored. */
|
||||
int *units_ignore;
|
||||
};
|
||||
|
||||
#define UNCORE_DISCOVERY_DOMAINS 2
|
||||
struct uncore_plat_init {
|
||||
void (*cpu_init)(void);
|
||||
int (*pci_init)(void);
|
||||
void (*mmio_init)(void);
|
||||
|
||||
struct uncore_discovery_domain domain[UNCORE_DISCOVERY_DOMAINS];
|
||||
};
|
||||
|
||||
struct intel_uncore_type {
|
||||
const char *name;
|
||||
int num_counters;
|
||||
@@ -597,6 +618,8 @@ extern struct pci_extra_dev *uncore_extra_pci_dev;
|
||||
extern struct event_constraint uncore_constraint_empty;
|
||||
extern int spr_uncore_units_ignore[];
|
||||
extern int gnr_uncore_units_ignore[];
|
||||
extern int dmr_uncore_imh_units_ignore[];
|
||||
extern int dmr_uncore_cbb_units_ignore[];
|
||||
|
||||
/* uncore_snb.c */
|
||||
int snb_uncore_pci_init(void);
|
||||
@@ -613,6 +636,7 @@ void adl_uncore_cpu_init(void);
|
||||
void lnl_uncore_cpu_init(void);
|
||||
void mtl_uncore_cpu_init(void);
|
||||
void ptl_uncore_cpu_init(void);
|
||||
void nvl_uncore_cpu_init(void);
|
||||
void tgl_uncore_mmio_init(void);
|
||||
void tgl_l_uncore_mmio_init(void);
|
||||
void adl_uncore_mmio_init(void);
|
||||
@@ -645,6 +669,8 @@ void spr_uncore_mmio_init(void);
|
||||
int gnr_uncore_pci_init(void);
|
||||
void gnr_uncore_cpu_init(void);
|
||||
void gnr_uncore_mmio_init(void);
|
||||
int dmr_uncore_pci_init(void);
|
||||
void dmr_uncore_mmio_init(void);
|
||||
|
||||
/* uncore_nhmex.c */
|
||||
void nhmex_uncore_cpu_init(void);
|
||||
|
||||
@@ -11,24 +11,6 @@
|
||||
static struct rb_root discovery_tables = RB_ROOT;
|
||||
static int num_discovered_types[UNCORE_ACCESS_MAX];
|
||||
|
||||
static bool has_generic_discovery_table(void)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
int dvsec;
|
||||
|
||||
dev = pci_get_device(PCI_VENDOR_ID_INTEL, UNCORE_DISCOVERY_TABLE_DEVICE, NULL);
|
||||
if (!dev)
|
||||
return false;
|
||||
|
||||
/* A discovery table device has the unique capability ID. */
|
||||
dvsec = pci_find_next_ext_capability(dev, 0, UNCORE_EXT_CAP_ID_DISCOVERY);
|
||||
pci_dev_put(dev);
|
||||
if (dvsec)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int logical_die_id;
|
||||
|
||||
static int get_device_die_id(struct pci_dev *dev)
|
||||
@@ -258,28 +240,30 @@ uncore_insert_box_info(struct uncore_unit_discovery *unit,
|
||||
}
|
||||
|
||||
static bool
|
||||
uncore_ignore_unit(struct uncore_unit_discovery *unit, int *ignore)
|
||||
uncore_ignore_unit(struct uncore_unit_discovery *unit,
|
||||
struct uncore_discovery_domain *domain)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (!ignore)
|
||||
if (!domain || !domain->units_ignore)
|
||||
return false;
|
||||
|
||||
for (i = 0; ignore[i] != UNCORE_IGNORE_END ; i++) {
|
||||
if (unit->box_type == ignore[i])
|
||||
for (i = 0; domain->units_ignore[i] != UNCORE_IGNORE_END ; i++) {
|
||||
if (unit->box_type == domain->units_ignore[i])
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int __parse_discovery_table(resource_size_t addr, int die,
|
||||
bool *parsed, int *ignore)
|
||||
static int __parse_discovery_table(struct uncore_discovery_domain *domain,
|
||||
resource_size_t addr, int die, bool *parsed)
|
||||
{
|
||||
struct uncore_global_discovery global;
|
||||
struct uncore_unit_discovery unit;
|
||||
void __iomem *io_addr;
|
||||
unsigned long size;
|
||||
int ret = 0;
|
||||
int i;
|
||||
|
||||
size = UNCORE_DISCOVERY_GLOBAL_MAP_SIZE;
|
||||
@@ -289,19 +273,24 @@ static int __parse_discovery_table(resource_size_t addr, int die,
|
||||
|
||||
/* Read Global Discovery State */
|
||||
memcpy_fromio(&global, io_addr, sizeof(struct uncore_global_discovery));
|
||||
iounmap(io_addr);
|
||||
|
||||
if (uncore_discovery_invalid_unit(global)) {
|
||||
pr_info("Invalid Global Discovery State: 0x%llx 0x%llx 0x%llx\n",
|
||||
global.table1, global.ctl, global.table3);
|
||||
iounmap(io_addr);
|
||||
return -EINVAL;
|
||||
}
|
||||
iounmap(io_addr);
|
||||
|
||||
size = (1 + global.max_units) * global.stride * 8;
|
||||
io_addr = ioremap(addr, size);
|
||||
if (!io_addr)
|
||||
return -ENOMEM;
|
||||
|
||||
if (domain->global_init && domain->global_init(global.ctl)) {
|
||||
ret = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Parsing Unit Discovery State */
|
||||
for (i = 0; i < global.max_units; i++) {
|
||||
memcpy_fromio(&unit, io_addr + (i + 1) * (global.stride * 8),
|
||||
@@ -313,20 +302,22 @@ static int __parse_discovery_table(resource_size_t addr, int die,
|
||||
if (unit.access_type >= UNCORE_ACCESS_MAX)
|
||||
continue;
|
||||
|
||||
if (uncore_ignore_unit(&unit, ignore))
|
||||
if (uncore_ignore_unit(&unit, domain))
|
||||
continue;
|
||||
|
||||
uncore_insert_box_info(&unit, die);
|
||||
}
|
||||
|
||||
*parsed = true;
|
||||
|
||||
out:
|
||||
iounmap(io_addr);
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int parse_discovery_table(struct pci_dev *dev, int die,
|
||||
u32 bar_offset, bool *parsed,
|
||||
int *ignore)
|
||||
static int parse_discovery_table(struct uncore_discovery_domain *domain,
|
||||
struct pci_dev *dev, int die,
|
||||
u32 bar_offset, bool *parsed)
|
||||
{
|
||||
resource_size_t addr;
|
||||
u32 val;
|
||||
@@ -346,20 +337,17 @@ static int parse_discovery_table(struct pci_dev *dev, int die,
|
||||
}
|
||||
#endif
|
||||
|
||||
return __parse_discovery_table(addr, die, parsed, ignore);
|
||||
return __parse_discovery_table(domain, addr, die, parsed);
|
||||
}
|
||||
|
||||
static bool intel_uncore_has_discovery_tables_pci(int *ignore)
|
||||
static bool uncore_discovery_pci(struct uncore_discovery_domain *domain)
|
||||
{
|
||||
u32 device, val, entry_id, bar_offset;
|
||||
int die, dvsec = 0, ret = true;
|
||||
struct pci_dev *dev = NULL;
|
||||
bool parsed = false;
|
||||
|
||||
if (has_generic_discovery_table())
|
||||
device = UNCORE_DISCOVERY_TABLE_DEVICE;
|
||||
else
|
||||
device = PCI_ANY_ID;
|
||||
device = domain->discovery_base;
|
||||
|
||||
/*
|
||||
* Start a new search and iterates through the list of
|
||||
@@ -382,10 +370,10 @@ static bool intel_uncore_has_discovery_tables_pci(int *ignore)
|
||||
(val & UNCORE_DISCOVERY_DVSEC2_BIR_MASK) * UNCORE_DISCOVERY_BIR_STEP;
|
||||
|
||||
die = get_device_die_id(dev);
|
||||
if (die < 0)
|
||||
if ((die < 0) || (die >= uncore_max_dies()))
|
||||
continue;
|
||||
|
||||
parse_discovery_table(dev, die, bar_offset, &parsed, ignore);
|
||||
parse_discovery_table(domain, dev, die, bar_offset, &parsed);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -398,7 +386,7 @@ err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static bool intel_uncore_has_discovery_tables_msr(int *ignore)
|
||||
static bool uncore_discovery_msr(struct uncore_discovery_domain *domain)
|
||||
{
|
||||
unsigned long *die_mask;
|
||||
bool parsed = false;
|
||||
@@ -416,13 +404,13 @@ static bool intel_uncore_has_discovery_tables_msr(int *ignore)
|
||||
if (__test_and_set_bit(die, die_mask))
|
||||
continue;
|
||||
|
||||
if (rdmsrl_safe_on_cpu(cpu, UNCORE_DISCOVERY_MSR, &base))
|
||||
if (rdmsrq_safe_on_cpu(cpu, domain->discovery_base, &base))
|
||||
continue;
|
||||
|
||||
if (!base)
|
||||
continue;
|
||||
|
||||
__parse_discovery_table(base, die, &parsed, ignore);
|
||||
__parse_discovery_table(domain, base, die, &parsed);
|
||||
}
|
||||
|
||||
cpus_read_unlock();
|
||||
@@ -431,10 +419,23 @@ static bool intel_uncore_has_discovery_tables_msr(int *ignore)
|
||||
return parsed;
|
||||
}
|
||||
|
||||
bool intel_uncore_has_discovery_tables(int *ignore)
|
||||
bool uncore_discovery(struct uncore_plat_init *init)
|
||||
{
|
||||
return intel_uncore_has_discovery_tables_msr(ignore) ||
|
||||
intel_uncore_has_discovery_tables_pci(ignore);
|
||||
struct uncore_discovery_domain *domain;
|
||||
bool ret = false;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < UNCORE_DISCOVERY_DOMAINS; i++) {
|
||||
domain = &init->domain[i];
|
||||
if (domain->discovery_base) {
|
||||
if (!domain->base_is_pci)
|
||||
ret |= uncore_discovery_msr(domain);
|
||||
else
|
||||
ret |= uncore_discovery_pci(domain);
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void intel_uncore_clear_discovery_tables(void)
|
||||
|
||||
@@ -2,9 +2,15 @@
|
||||
|
||||
/* Store the full address of the global discovery table */
|
||||
#define UNCORE_DISCOVERY_MSR 0x201e
|
||||
/* Base address of uncore perfmon discovery table for CBB domain */
|
||||
#define CBB_UNCORE_DISCOVERY_MSR 0x710
|
||||
/* Base address of uncore perfmon discovery table for the package */
|
||||
#define PACKAGE_UNCORE_DISCOVERY_MSR 0x711
|
||||
|
||||
/* Generic device ID of a discovery table device */
|
||||
#define UNCORE_DISCOVERY_TABLE_DEVICE 0x09a7
|
||||
/* Device ID used on DMR */
|
||||
#define DMR_UNCORE_DISCOVERY_TABLE_DEVICE 0x09a1
|
||||
/* Capability ID for a discovery table device */
|
||||
#define UNCORE_EXT_CAP_ID_DISCOVERY 0x23
|
||||
/* First DVSEC offset */
|
||||
@@ -136,7 +142,7 @@ struct intel_uncore_discovery_type {
|
||||
u16 num_units; /* number of units */
|
||||
};
|
||||
|
||||
bool intel_uncore_has_discovery_tables(int *ignore);
|
||||
bool uncore_discovery(struct uncore_plat_init *init);
|
||||
void intel_uncore_clear_discovery_tables(void);
|
||||
void intel_uncore_generic_uncore_cpu_init(void);
|
||||
int intel_uncore_generic_uncore_pci_init(void);
|
||||
|
||||
@@ -244,6 +244,30 @@
|
||||
#define MTL_UNC_HBO_CTR 0x2048
|
||||
#define MTL_UNC_HBO_CTRL 0x2042
|
||||
|
||||
/* PTL Low Power Bridge register */
|
||||
#define PTL_UNC_IA_CORE_BRIDGE_PER_CTR0 0x2028
|
||||
#define PTL_UNC_IA_CORE_BRIDGE_PERFEVTSEL0 0x2022
|
||||
|
||||
/* PTL Santa register */
|
||||
#define PTL_UNC_SANTA_CTR0 0x2418
|
||||
#define PTL_UNC_SANTA_CTRL0 0x2412
|
||||
|
||||
/* PTL cNCU register */
|
||||
#define PTL_UNC_CNCU_MSR_OFFSET 0x140
|
||||
|
||||
/* NVL cNCU register */
|
||||
#define NVL_UNC_CNCU_BOX_CTL 0x202e
|
||||
#define NVL_UNC_CNCU_FIXED_CTR 0x2028
|
||||
#define NVL_UNC_CNCU_FIXED_CTRL 0x2022
|
||||
|
||||
/* NVL SANTA register */
|
||||
#define NVL_UNC_SANTA_CTR0 0x2048
|
||||
#define NVL_UNC_SANTA_CTRL0 0x2042
|
||||
|
||||
/* NVL CBOX register */
|
||||
#define NVL_UNC_CBOX_PER_CTR0 0x2108
|
||||
#define NVL_UNC_CBOX_PERFEVTSEL0 0x2102
|
||||
|
||||
DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(chmask, chmask, "config:8-11");
|
||||
@@ -1920,8 +1944,36 @@ void ptl_uncore_mmio_init(void)
|
||||
ptl_uncores);
|
||||
}
|
||||
|
||||
static struct intel_uncore_type ptl_uncore_ia_core_bridge = {
|
||||
.name = "ia_core_bridge",
|
||||
.num_counters = 2,
|
||||
.num_boxes = 1,
|
||||
.perf_ctr_bits = 48,
|
||||
.perf_ctr = PTL_UNC_IA_CORE_BRIDGE_PER_CTR0,
|
||||
.event_ctl = PTL_UNC_IA_CORE_BRIDGE_PERFEVTSEL0,
|
||||
.event_mask = ADL_UNC_RAW_EVENT_MASK,
|
||||
.ops = &icl_uncore_msr_ops,
|
||||
.format_group = &adl_uncore_format_group,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type ptl_uncore_santa = {
|
||||
.name = "santa",
|
||||
.num_counters = 2,
|
||||
.num_boxes = 2,
|
||||
.perf_ctr_bits = 48,
|
||||
.perf_ctr = PTL_UNC_SANTA_CTR0,
|
||||
.event_ctl = PTL_UNC_SANTA_CTRL0,
|
||||
.event_mask = ADL_UNC_RAW_EVENT_MASK,
|
||||
.msr_offset = SNB_UNC_CBO_MSR_OFFSET,
|
||||
.ops = &icl_uncore_msr_ops,
|
||||
.format_group = &adl_uncore_format_group,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type *ptl_msr_uncores[] = {
|
||||
&mtl_uncore_cbox,
|
||||
&ptl_uncore_ia_core_bridge,
|
||||
&ptl_uncore_santa,
|
||||
&mtl_uncore_cncu,
|
||||
NULL
|
||||
};
|
||||
|
||||
@@ -1929,7 +1981,40 @@ void ptl_uncore_cpu_init(void)
|
||||
{
|
||||
mtl_uncore_cbox.num_boxes = 6;
|
||||
mtl_uncore_cbox.ops = &lnl_uncore_msr_ops;
|
||||
|
||||
mtl_uncore_cncu.num_counters = 2;
|
||||
mtl_uncore_cncu.num_boxes = 2;
|
||||
mtl_uncore_cncu.msr_offset = PTL_UNC_CNCU_MSR_OFFSET;
|
||||
mtl_uncore_cncu.single_fixed = 0;
|
||||
|
||||
uncore_msr_uncores = ptl_msr_uncores;
|
||||
}
|
||||
|
||||
/* end of Panther Lake uncore support */
|
||||
|
||||
/* Nova Lake uncore support */
|
||||
|
||||
static struct intel_uncore_type *nvl_msr_uncores[] = {
|
||||
&mtl_uncore_cbox,
|
||||
&ptl_uncore_santa,
|
||||
&mtl_uncore_cncu,
|
||||
NULL
|
||||
};
|
||||
|
||||
void nvl_uncore_cpu_init(void)
|
||||
{
|
||||
mtl_uncore_cbox.num_boxes = 12;
|
||||
mtl_uncore_cbox.perf_ctr = NVL_UNC_CBOX_PER_CTR0;
|
||||
mtl_uncore_cbox.event_ctl = NVL_UNC_CBOX_PERFEVTSEL0;
|
||||
|
||||
ptl_uncore_santa.perf_ctr = NVL_UNC_SANTA_CTR0;
|
||||
ptl_uncore_santa.event_ctl = NVL_UNC_SANTA_CTRL0;
|
||||
|
||||
mtl_uncore_cncu.box_ctl = NVL_UNC_CNCU_BOX_CTL;
|
||||
mtl_uncore_cncu.fixed_ctr = NVL_UNC_CNCU_FIXED_CTR;
|
||||
mtl_uncore_cncu.fixed_ctl = NVL_UNC_CNCU_FIXED_CTRL;
|
||||
|
||||
uncore_msr_uncores = nvl_msr_uncores;
|
||||
}
|
||||
|
||||
/* end of Nova Lake uncore support */
|
||||
|
||||
@@ -470,6 +470,18 @@
|
||||
|
||||
#define SPR_C0_MSR_PMON_BOX_FILTER0 0x200e
|
||||
|
||||
/* DMR */
|
||||
#define DMR_IMH1_HIOP_MMIO_BASE 0x1ffff6ae7000
|
||||
#define DMR_HIOP_MMIO_SIZE 0x8000
|
||||
#define DMR_CXLCM_EVENT_MASK_EXT 0xf
|
||||
#define DMR_HAMVF_EVENT_MASK_EXT 0xffffffff
|
||||
#define DMR_PCIE4_EVENT_MASK_EXT 0xffffff
|
||||
|
||||
#define UNCORE_DMR_ITC 0x30
|
||||
|
||||
#define DMR_IMC_PMON_FIXED_CTR 0x18
|
||||
#define DMR_IMC_PMON_FIXED_CTL 0x10
|
||||
|
||||
DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(event2, event, "config:0-6");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
|
||||
@@ -485,6 +497,10 @@ DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(tid_en2, tid_en, "config:16");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(inv2, inv, "config:21");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(thresh_ext, thresh_ext, "config:32-35");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(thresh10, thresh, "config:23-32");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(thresh9_2, thresh, "config:23-31");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(thresh9, thresh, "config:24-35");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(thresh6, thresh, "config:24-29");
|
||||
@@ -493,6 +509,13 @@ DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(occ_edge_det, occ_edge_det, "config:31");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(port_en, port_en, "config:32-35");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(rs3_sel, rs3_sel, "config:36");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(rx_sel, rx_sel, "config:37");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(tx_sel, tx_sel, "config:38");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(iep_sel, iep_sel, "config:39");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(vc_sel, vc_sel, "config:40-47");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(port_sel, port_sel, "config:48-55");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(ch_mask, ch_mask, "config:36-43");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(ch_mask2, ch_mask, "config:36-47");
|
||||
DEFINE_UNCORE_FORMAT_ATTR(fc_mask, fc_mask, "config:44-46");
|
||||
@@ -812,76 +835,37 @@ static struct intel_uncore_ops snbep_uncore_pci_ops = {
|
||||
static struct event_constraint snbep_uncore_cbox_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x04, 0x5, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x1b, 0xc),
|
||||
UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
|
||||
UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
|
||||
UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x12, 0x13, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x1b, 0x1e, 0xc),
|
||||
UNCORE_EVENT_CONSTRAINT(0x1f, 0xe),
|
||||
UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x31, 0x35, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x37, 0x39, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
static struct event_constraint snbep_uncore_r2pcie_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x11, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x24, 0x26, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x32, 0x34, 0x3),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x12, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2a, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x20, 0x26, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x34, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x36, 0x39, 0x3),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
@@ -1474,13 +1458,7 @@ static int snbep_pci2phy_map_init(int devid, int nodeid_loc, int idmap_loc, bool
|
||||
}
|
||||
|
||||
map->pbus_to_dieid[bus] = die_id = uncore_device_to_die(ubox_dev);
|
||||
|
||||
raw_spin_unlock(&pci2phy_map_lock);
|
||||
|
||||
if (WARN_ON_ONCE(die_id == -1)) {
|
||||
err = -EINVAL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -3010,24 +2988,15 @@ static struct intel_uncore_type hswep_uncore_qpi = {
|
||||
};
|
||||
|
||||
static struct event_constraint hswep_uncore_r2pcie_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x11, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x24, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x23, 0x25, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x27, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x29, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2a, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x2b, 0x2d, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x32, 0x35, 0x3),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
@@ -3042,38 +3011,17 @@ static struct intel_uncore_type hswep_uncore_r2pcie = {
|
||||
|
||||
static struct event_constraint hswep_uncore_r3qpi_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT(0x01, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x07, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x08, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x09, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x0a, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x7, 0x0a, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x0e, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x12, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x15, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x1f, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x14, 0x15, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x1f, 0x23, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x25, 0x26, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x29, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x2c, 0x2f, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x31, 0x34, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x36, 0x39, 0x3),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
@@ -3347,8 +3295,7 @@ static struct event_constraint bdx_uncore_r2pcie_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x2c, 0x2d, 0x3),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
@@ -3363,35 +3310,18 @@ static struct intel_uncore_type bdx_uncore_r2pcie = {
|
||||
|
||||
static struct event_constraint bdx_uncore_r3qpi_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT(0x01, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x07, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x08, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x09, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x0a, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x07, 0x0a, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x0e, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x11, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x15, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x1f, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x14, 0x15, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x1f, 0x23, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x29, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x2c, 0x2f, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x33, 0x34, 0x3),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x36, 0x39, 0x3),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
@@ -3698,8 +3628,7 @@ static struct event_constraint skx_uncore_iio_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT(0x95, 0xc),
|
||||
UNCORE_EVENT_CONSTRAINT(0xc0, 0xc),
|
||||
UNCORE_EVENT_CONSTRAINT(0xc5, 0xc),
|
||||
UNCORE_EVENT_CONSTRAINT(0xd4, 0xc),
|
||||
UNCORE_EVENT_CONSTRAINT(0xd5, 0xc),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0xd4, 0xd5, 0xc),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
@@ -4048,34 +3977,24 @@ static struct freerunning_counters skx_iio_freerunning[] = {
|
||||
[SKX_IIO_MSR_UTIL] = { 0xb08, 0x1, 0x10, 8, 36 },
|
||||
};
|
||||
|
||||
#define INTEL_UNCORE_FR_EVENT_DESC(name, umask, scl) \
|
||||
INTEL_UNCORE_EVENT_DESC(name, \
|
||||
"event=0xff,umask=" __stringify(umask)),\
|
||||
INTEL_UNCORE_EVENT_DESC(name.scale, __stringify(scl)), \
|
||||
INTEL_UNCORE_EVENT_DESC(name.unit, "MiB")
|
||||
|
||||
static struct uncore_event_desc skx_uncore_iio_freerunning_events[] = {
|
||||
/* Free-Running IO CLOCKS Counter */
|
||||
INTEL_UNCORE_EVENT_DESC(ioclk, "event=0xff,umask=0x10"),
|
||||
/* Free-Running IIO BANDWIDTH Counters */
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port0, "event=0xff,umask=0x20"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale, "3.814697266e-6"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port0.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port1, "event=0xff,umask=0x21"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale, "3.814697266e-6"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port1.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port2, "event=0xff,umask=0x22"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale, "3.814697266e-6"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port2.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port3, "event=0xff,umask=0x23"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale, "3.814697266e-6"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port3.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_out_port0, "event=0xff,umask=0x24"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_out_port0.scale, "3.814697266e-6"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_out_port0.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_out_port1, "event=0xff,umask=0x25"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_out_port1.scale, "3.814697266e-6"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_out_port1.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_out_port2, "event=0xff,umask=0x26"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_out_port2.scale, "3.814697266e-6"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_out_port2.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_out_port3, "event=0xff,umask=0x27"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_out_port3.scale, "3.814697266e-6"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_out_port3.unit, "MiB"),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port0, 0x24, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port1, 0x25, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port2, 0x26, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port3, 0x27, 3.814697266e-6),
|
||||
/* Free-running IIO UTILIZATION Counters */
|
||||
INTEL_UNCORE_EVENT_DESC(util_in_port0, "event=0xff,umask=0x30"),
|
||||
INTEL_UNCORE_EVENT_DESC(util_out_port0, "event=0xff,umask=0x31"),
|
||||
@@ -4465,14 +4384,9 @@ static struct intel_uncore_type skx_uncore_m2pcie = {
|
||||
};
|
||||
|
||||
static struct event_constraint skx_uncore_m3upi_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT(0x1d, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x1e, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x1d, 0x1e, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x40, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x4e, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x4f, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x50, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x51, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x52, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x4e, 0x52, 0x7),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
@@ -4890,30 +4804,14 @@ static struct uncore_event_desc snr_uncore_iio_freerunning_events[] = {
|
||||
/* Free-Running IIO CLOCKS Counter */
|
||||
INTEL_UNCORE_EVENT_DESC(ioclk, "event=0xff,umask=0x10"),
|
||||
/* Free-Running IIO BANDWIDTH IN Counters */
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port0, "event=0xff,umask=0x20"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale, "3.0517578125e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port0.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port1, "event=0xff,umask=0x21"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale, "3.0517578125e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port1.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port2, "event=0xff,umask=0x22"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale, "3.0517578125e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port2.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port3, "event=0xff,umask=0x23"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale, "3.0517578125e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port3.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port4, "event=0xff,umask=0x24"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port4.scale, "3.0517578125e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port4.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port5, "event=0xff,umask=0x25"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port5.scale, "3.0517578125e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port5.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port6, "event=0xff,umask=0x26"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port6.scale, "3.0517578125e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port6.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port7, "event=0xff,umask=0x27"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port7.scale, "3.0517578125e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(bw_in_port7.unit, "MiB"),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, 3.0517578125e-5),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, 3.0517578125e-5),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, 3.0517578125e-5),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, 3.0517578125e-5),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port4, 0x24, 3.0517578125e-5),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port5, 0x25, 3.0517578125e-5),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port6, 0x26, 3.0517578125e-5),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port7, 0x27, 3.0517578125e-5),
|
||||
{ /* end: all zeroes */ },
|
||||
};
|
||||
|
||||
@@ -5246,12 +5144,8 @@ static struct freerunning_counters snr_imc_freerunning[] = {
|
||||
static struct uncore_event_desc snr_uncore_imc_freerunning_events[] = {
|
||||
INTEL_UNCORE_EVENT_DESC(dclk, "event=0xff,umask=0x10"),
|
||||
|
||||
INTEL_UNCORE_EVENT_DESC(read, "event=0xff,umask=0x20"),
|
||||
INTEL_UNCORE_EVENT_DESC(read.scale, "6.103515625e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(read.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(write, "event=0xff,umask=0x21"),
|
||||
INTEL_UNCORE_EVENT_DESC(write.scale, "6.103515625e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(write.unit, "MiB"),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(read, 0x20, 6.103515625e-5),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(write, 0x21, 6.103515625e-5),
|
||||
{ /* end: all zeroes */ },
|
||||
};
|
||||
|
||||
@@ -5658,14 +5552,9 @@ static struct intel_uncore_type icx_uncore_upi = {
|
||||
};
|
||||
|
||||
static struct event_constraint icx_uncore_m3upi_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT(0x1c, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x1d, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x1e, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x1f, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x1c, 0x1f, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x40, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x4e, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x4f, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT(0x50, 0x7),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x4e, 0x50, 0x7),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
@@ -5816,19 +5705,10 @@ static struct freerunning_counters icx_imc_freerunning[] = {
|
||||
static struct uncore_event_desc icx_uncore_imc_freerunning_events[] = {
|
||||
INTEL_UNCORE_EVENT_DESC(dclk, "event=0xff,umask=0x10"),
|
||||
|
||||
INTEL_UNCORE_EVENT_DESC(read, "event=0xff,umask=0x20"),
|
||||
INTEL_UNCORE_EVENT_DESC(read.scale, "6.103515625e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(read.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(write, "event=0xff,umask=0x21"),
|
||||
INTEL_UNCORE_EVENT_DESC(write.scale, "6.103515625e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(write.unit, "MiB"),
|
||||
|
||||
INTEL_UNCORE_EVENT_DESC(ddrt_read, "event=0xff,umask=0x30"),
|
||||
INTEL_UNCORE_EVENT_DESC(ddrt_read.scale, "6.103515625e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(ddrt_read.unit, "MiB"),
|
||||
INTEL_UNCORE_EVENT_DESC(ddrt_write, "event=0xff,umask=0x31"),
|
||||
INTEL_UNCORE_EVENT_DESC(ddrt_write.scale, "6.103515625e-5"),
|
||||
INTEL_UNCORE_EVENT_DESC(ddrt_write.unit, "MiB"),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(read, 0x20, 6.103515625e-5),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(write, 0x21, 6.103515625e-5),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(ddrt_read, 0x30, 6.103515625e-5),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(ddrt_write, 0x31, 6.103515625e-5),
|
||||
{ /* end: all zeroes */ },
|
||||
};
|
||||
|
||||
@@ -6157,10 +6037,7 @@ static struct intel_uncore_ops spr_uncore_mmio_offs8_ops = {
|
||||
static struct event_constraint spr_uncore_cxlcm_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT(0x02, 0x0f),
|
||||
UNCORE_EVENT_CONSTRAINT(0x05, 0x0f),
|
||||
UNCORE_EVENT_CONSTRAINT(0x40, 0xf0),
|
||||
UNCORE_EVENT_CONSTRAINT(0x41, 0xf0),
|
||||
UNCORE_EVENT_CONSTRAINT(0x42, 0xf0),
|
||||
UNCORE_EVENT_CONSTRAINT(0x43, 0xf0),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x40, 0x43, 0xf0),
|
||||
UNCORE_EVENT_CONSTRAINT(0x4b, 0xf0),
|
||||
UNCORE_EVENT_CONSTRAINT(0x52, 0xf0),
|
||||
EVENT_CONSTRAINT_END
|
||||
@@ -6461,7 +6338,11 @@ static int uncore_type_max_boxes(struct intel_uncore_type **types,
|
||||
for (node = rb_first(type->boxes); node; node = rb_next(node)) {
|
||||
unit = rb_entry(node, struct intel_uncore_discovery_unit, node);
|
||||
|
||||
if (unit->id > max)
|
||||
/*
|
||||
* on DMR IMH2, the unit id starts from 0x8000,
|
||||
* and we don't need to count it.
|
||||
*/
|
||||
if ((unit->id > max) && (unit->id < 0x8000))
|
||||
max = unit->id;
|
||||
}
|
||||
return max + 1;
|
||||
@@ -6532,7 +6413,7 @@ static void spr_update_device_location(int type_id)
|
||||
|
||||
while ((dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, dev)) != NULL) {
|
||||
|
||||
die = uncore_device_to_die(dev);
|
||||
die = uncore_pcibus_to_dieid(dev->bus);
|
||||
if (die < 0)
|
||||
continue;
|
||||
|
||||
@@ -6556,6 +6437,11 @@ static void spr_update_device_location(int type_id)
|
||||
|
||||
int spr_uncore_pci_init(void)
|
||||
{
|
||||
int ret = snbep_pci2phy_map_init(0x3250, SKX_CPUNODEID, SKX_GIDNIDMAP, true);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* The discovery table of UPI on some SPR variant is broken,
|
||||
* which impacts the detection of both UPI and M3UPI uncore PMON.
|
||||
@@ -6708,3 +6594,386 @@ void gnr_uncore_mmio_init(void)
|
||||
}
|
||||
|
||||
/* end of GNR uncore support */
|
||||
|
||||
/* DMR uncore support */
|
||||
#define UNCORE_DMR_NUM_UNCORE_TYPES 52
|
||||
|
||||
static struct attribute *dmr_imc_uncore_formats_attr[] = {
|
||||
&format_attr_event.attr,
|
||||
&format_attr_umask.attr,
|
||||
&format_attr_edge.attr,
|
||||
&format_attr_inv.attr,
|
||||
&format_attr_thresh10.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const struct attribute_group dmr_imc_uncore_format_group = {
|
||||
.name = "format",
|
||||
.attrs = dmr_imc_uncore_formats_attr,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_imc = {
|
||||
.name = "imc",
|
||||
.fixed_ctr_bits = 48,
|
||||
.fixed_ctr = DMR_IMC_PMON_FIXED_CTR,
|
||||
.fixed_ctl = DMR_IMC_PMON_FIXED_CTL,
|
||||
.ops = &spr_uncore_mmio_ops,
|
||||
.format_group = &dmr_imc_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct attribute *dmr_sca_uncore_formats_attr[] = {
|
||||
&format_attr_event.attr,
|
||||
&format_attr_umask_ext5.attr,
|
||||
&format_attr_edge.attr,
|
||||
&format_attr_inv.attr,
|
||||
&format_attr_thresh8.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const struct attribute_group dmr_sca_uncore_format_group = {
|
||||
.name = "format",
|
||||
.attrs = dmr_sca_uncore_formats_attr,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_sca = {
|
||||
.name = "sca",
|
||||
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
|
||||
.format_group = &dmr_sca_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct attribute *dmr_cxlcm_uncore_formats_attr[] = {
|
||||
&format_attr_event.attr,
|
||||
&format_attr_umask.attr,
|
||||
&format_attr_edge.attr,
|
||||
&format_attr_inv2.attr,
|
||||
&format_attr_thresh9_2.attr,
|
||||
&format_attr_port_en.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const struct attribute_group dmr_cxlcm_uncore_format_group = {
|
||||
.name = "format",
|
||||
.attrs = dmr_cxlcm_uncore_formats_attr,
|
||||
};
|
||||
|
||||
static struct event_constraint dmr_uncore_cxlcm_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x1, 0x24, 0x0f),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x41, 0x41, 0xf0),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x50, 0x5e, 0xf0),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x60, 0x61, 0xf0),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_cxlcm = {
|
||||
.name = "cxlcm",
|
||||
.event_mask = GENERIC_PMON_RAW_EVENT_MASK,
|
||||
.event_mask_ext = DMR_CXLCM_EVENT_MASK_EXT,
|
||||
.constraints = dmr_uncore_cxlcm_constraints,
|
||||
.format_group = &dmr_cxlcm_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_hamvf = {
|
||||
.name = "hamvf",
|
||||
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
|
||||
.format_group = &dmr_sca_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct event_constraint dmr_uncore_cbo_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT_RANGE(0x19, 0x1a, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x1f, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x21, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
|
||||
UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_cbo = {
|
||||
.name = "cbo",
|
||||
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
|
||||
.constraints = dmr_uncore_cbo_constraints,
|
||||
.format_group = &dmr_sca_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_santa = {
|
||||
.name = "santa",
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_cncu = {
|
||||
.name = "cncu",
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_sncu = {
|
||||
.name = "sncu",
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_ula = {
|
||||
.name = "ula",
|
||||
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
|
||||
.format_group = &dmr_sca_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_dda = {
|
||||
.name = "dda",
|
||||
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
|
||||
.format_group = &dmr_sca_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct event_constraint dmr_uncore_sbo_constraints[] = {
|
||||
UNCORE_EVENT_CONSTRAINT(0x1f, 0x01),
|
||||
UNCORE_EVENT_CONSTRAINT(0x25, 0x01),
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_sbo = {
|
||||
.name = "sbo",
|
||||
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
|
||||
.constraints = dmr_uncore_sbo_constraints,
|
||||
.format_group = &dmr_sca_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_ubr = {
|
||||
.name = "ubr",
|
||||
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
|
||||
.format_group = &dmr_sca_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct attribute *dmr_pcie4_uncore_formats_attr[] = {
|
||||
&format_attr_event.attr,
|
||||
&format_attr_umask.attr,
|
||||
&format_attr_edge.attr,
|
||||
&format_attr_inv.attr,
|
||||
&format_attr_thresh8.attr,
|
||||
&format_attr_thresh_ext.attr,
|
||||
&format_attr_rs3_sel.attr,
|
||||
&format_attr_rx_sel.attr,
|
||||
&format_attr_tx_sel.attr,
|
||||
&format_attr_iep_sel.attr,
|
||||
&format_attr_vc_sel.attr,
|
||||
&format_attr_port_sel.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const struct attribute_group dmr_pcie4_uncore_format_group = {
|
||||
.name = "format",
|
||||
.attrs = dmr_pcie4_uncore_formats_attr,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_pcie4 = {
|
||||
.name = "pcie4",
|
||||
.event_mask_ext = DMR_PCIE4_EVENT_MASK_EXT,
|
||||
.format_group = &dmr_pcie4_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_crs = {
|
||||
.name = "crs",
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_cpc = {
|
||||
.name = "cpc",
|
||||
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
|
||||
.format_group = &dmr_sca_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_itc = {
|
||||
.name = "itc",
|
||||
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
|
||||
.format_group = &dmr_sca_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_otc = {
|
||||
.name = "otc",
|
||||
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
|
||||
.format_group = &dmr_sca_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_cms = {
|
||||
.name = "cms",
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_pcie6 = {
|
||||
.name = "pcie6",
|
||||
.event_mask_ext = DMR_PCIE4_EVENT_MASK_EXT,
|
||||
.format_group = &dmr_pcie4_uncore_format_group,
|
||||
.attr_update = uncore_alias_groups,
|
||||
};
|
||||
|
||||
static struct intel_uncore_type *dmr_uncores[UNCORE_DMR_NUM_UNCORE_TYPES] = {
|
||||
NULL, NULL, NULL, NULL,
|
||||
&spr_uncore_pcu,
|
||||
&gnr_uncore_ubox,
|
||||
&dmr_uncore_imc,
|
||||
NULL,
|
||||
NULL, NULL, NULL, NULL,
|
||||
NULL, NULL, NULL, NULL,
|
||||
NULL, NULL, NULL, NULL,
|
||||
NULL, NULL, NULL,
|
||||
&dmr_uncore_sca,
|
||||
&dmr_uncore_cxlcm,
|
||||
NULL, NULL, NULL,
|
||||
NULL, NULL,
|
||||
&dmr_uncore_hamvf,
|
||||
&dmr_uncore_cbo,
|
||||
&dmr_uncore_santa,
|
||||
&dmr_uncore_cncu,
|
||||
&dmr_uncore_sncu,
|
||||
&dmr_uncore_ula,
|
||||
&dmr_uncore_dda,
|
||||
NULL,
|
||||
&dmr_uncore_sbo,
|
||||
NULL,
|
||||
NULL, NULL, NULL,
|
||||
&dmr_uncore_ubr,
|
||||
NULL,
|
||||
&dmr_uncore_pcie4,
|
||||
&dmr_uncore_crs,
|
||||
&dmr_uncore_cpc,
|
||||
&dmr_uncore_itc,
|
||||
&dmr_uncore_otc,
|
||||
&dmr_uncore_cms,
|
||||
&dmr_uncore_pcie6,
|
||||
};
|
||||
|
||||
int dmr_uncore_imh_units_ignore[] = {
|
||||
0x13, /* MSE */
|
||||
UNCORE_IGNORE_END
|
||||
};
|
||||
|
||||
int dmr_uncore_cbb_units_ignore[] = {
|
||||
0x25, /* SB2UCIE */
|
||||
UNCORE_IGNORE_END
|
||||
};
|
||||
|
||||
static unsigned int dmr_iio_freerunning_box_offsets[] = {
|
||||
0x0, 0x8000, 0x18000, 0x20000
|
||||
};
|
||||
|
||||
static void dmr_uncore_freerunning_init_box(struct intel_uncore_box *box)
|
||||
{
|
||||
struct intel_uncore_type *type = box->pmu->type;
|
||||
u64 mmio_base;
|
||||
|
||||
if (box->pmu->pmu_idx >= type->num_boxes)
|
||||
return;
|
||||
|
||||
mmio_base = DMR_IMH1_HIOP_MMIO_BASE;
|
||||
mmio_base += dmr_iio_freerunning_box_offsets[box->pmu->pmu_idx];
|
||||
|
||||
box->io_addr = ioremap(mmio_base, type->mmio_map_size);
|
||||
if (!box->io_addr)
|
||||
pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name);
|
||||
}
|
||||
|
||||
static struct intel_uncore_ops dmr_uncore_freerunning_ops = {
|
||||
.init_box = dmr_uncore_freerunning_init_box,
|
||||
.exit_box = uncore_mmio_exit_box,
|
||||
.read_counter = uncore_mmio_read_counter,
|
||||
.hw_config = uncore_freerunning_hw_config,
|
||||
};
|
||||
|
||||
enum perf_uncore_dmr_iio_freerunning_type_id {
|
||||
DMR_ITC_INB_DATA_BW,
|
||||
DMR_ITC_BW_IN,
|
||||
DMR_OTC_BW_OUT,
|
||||
DMR_OTC_CLOCK_TICKS,
|
||||
|
||||
DMR_IIO_FREERUNNING_TYPE_MAX,
|
||||
};
|
||||
|
||||
static struct freerunning_counters dmr_iio_freerunning[] = {
|
||||
[DMR_ITC_INB_DATA_BW] = { 0x4d40, 0x8, 0, 8, 48},
|
||||
[DMR_ITC_BW_IN] = { 0x6b00, 0x8, 0, 8, 48},
|
||||
[DMR_OTC_BW_OUT] = { 0x6b60, 0x8, 0, 8, 48},
|
||||
[DMR_OTC_CLOCK_TICKS] = { 0x6bb0, 0x8, 0, 1, 48},
|
||||
};
|
||||
|
||||
static struct uncore_event_desc dmr_uncore_iio_freerunning_events[] = {
|
||||
/* ITC Free Running Data BW counter for inbound traffic */
|
||||
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port0, 0x10, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port1, 0x11, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port2, 0x12, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port3, 0x13, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port4, 0x14, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port5, 0x15, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port6, 0x16, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(inb_data_port7, 0x17, 3.814697266e-6),
|
||||
|
||||
/* ITC Free Running BW IN counters */
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port4, 0x24, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port5, 0x25, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port6, 0x26, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_in_port7, 0x27, 3.814697266e-6),
|
||||
|
||||
/* ITC Free Running BW OUT counters */
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port0, 0x30, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port1, 0x31, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port2, 0x32, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port3, 0x33, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port4, 0x34, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port5, 0x35, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port6, 0x36, 3.814697266e-6),
|
||||
INTEL_UNCORE_FR_EVENT_DESC(bw_out_port7, 0x37, 3.814697266e-6),
|
||||
|
||||
/* Free Running Clock Counter */
|
||||
INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x40"),
|
||||
{ /* end: all zeroes */ },
|
||||
};
|
||||
|
||||
static struct intel_uncore_type dmr_uncore_iio_free_running = {
|
||||
.name = "iio_free_running",
|
||||
.num_counters = 25,
|
||||
.mmio_map_size = DMR_HIOP_MMIO_SIZE,
|
||||
.num_freerunning_types = DMR_IIO_FREERUNNING_TYPE_MAX,
|
||||
.freerunning = dmr_iio_freerunning,
|
||||
.ops = &dmr_uncore_freerunning_ops,
|
||||
.event_descs = dmr_uncore_iio_freerunning_events,
|
||||
.format_group = &skx_uncore_iio_freerunning_format_group,
|
||||
};
|
||||
|
||||
#define UNCORE_DMR_MMIO_EXTRA_UNCORES 1
|
||||
static struct intel_uncore_type *dmr_mmio_uncores[UNCORE_DMR_MMIO_EXTRA_UNCORES] = {
|
||||
&dmr_uncore_iio_free_running,
|
||||
};
|
||||
|
||||
int dmr_uncore_pci_init(void)
|
||||
{
|
||||
uncore_pci_uncores = uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL,
|
||||
UNCORE_DMR_NUM_UNCORE_TYPES,
|
||||
dmr_uncores);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dmr_uncore_mmio_init(void)
|
||||
{
|
||||
uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO,
|
||||
UNCORE_DMR_MMIO_EXTRA_UNCORES,
|
||||
dmr_mmio_uncores,
|
||||
UNCORE_DMR_NUM_UNCORE_TYPES,
|
||||
dmr_uncores);
|
||||
|
||||
dmr_uncore_iio_free_running.num_boxes =
|
||||
uncore_type_max_boxes(uncore_mmio_uncores, UNCORE_DMR_ITC);
|
||||
}
|
||||
/* end of DMR uncore support */
|
||||
|
||||
@@ -44,6 +44,10 @@ enum extra_reg_type {
|
||||
EXTRA_REG_FE = 4, /* fe_* */
|
||||
EXTRA_REG_SNOOP_0 = 5, /* snoop response 0 */
|
||||
EXTRA_REG_SNOOP_1 = 6, /* snoop response 1 */
|
||||
EXTRA_REG_OMR_0 = 7, /* OMR 0 */
|
||||
EXTRA_REG_OMR_1 = 8, /* OMR 1 */
|
||||
EXTRA_REG_OMR_2 = 9, /* OMR 2 */
|
||||
EXTRA_REG_OMR_3 = 10, /* OMR 3 */
|
||||
|
||||
EXTRA_REG_MAX /* number of entries needed */
|
||||
};
|
||||
@@ -132,6 +136,16 @@ static inline bool is_acr_event_group(struct perf_event *event)
|
||||
return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR);
|
||||
}
|
||||
|
||||
static inline bool is_acr_self_reload_event(struct perf_event *event)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
|
||||
if (hwc->idx < 0)
|
||||
return false;
|
||||
|
||||
return test_bit(hwc->idx, (unsigned long *)&hwc->config1);
|
||||
}
|
||||
|
||||
struct amd_nb {
|
||||
int nb_id; /* NorthBridge id */
|
||||
int refcnt; /* reference count */
|
||||
@@ -182,6 +196,13 @@ struct amd_nb {
|
||||
(1ULL << PERF_REG_X86_R14) | \
|
||||
(1ULL << PERF_REG_X86_R15))
|
||||
|
||||
/* user space rdpmc control values */
|
||||
enum {
|
||||
X86_USER_RDPMC_NEVER_ENABLE = 0,
|
||||
X86_USER_RDPMC_CONDITIONAL_ENABLE = 1,
|
||||
X86_USER_RDPMC_ALWAYS_ENABLE = 2,
|
||||
};
|
||||
|
||||
/*
|
||||
* Per register state.
|
||||
*/
|
||||
@@ -1098,6 +1119,7 @@ do { \
|
||||
#define PMU_FL_RETIRE_LATENCY 0x200 /* Support Retire Latency in PEBS */
|
||||
#define PMU_FL_BR_CNTR 0x400 /* Support branch counter logging */
|
||||
#define PMU_FL_DYN_CONSTRAINT 0x800 /* Needs dynamic constraint */
|
||||
#define PMU_FL_HAS_OMR 0x1000 /* has 4 equivalent OMR regs */
|
||||
|
||||
#define EVENT_VAR(_id) event_attr_##_id
|
||||
#define EVENT_PTR(_id) &event_attr_##_id.attr.attr
|
||||
@@ -1320,6 +1342,12 @@ static inline u64 x86_pmu_get_event_config(struct perf_event *event)
|
||||
return event->attr.config & hybrid(event->pmu, config_mask);
|
||||
}
|
||||
|
||||
static inline bool x86_pmu_has_rdpmc_user_disable(struct pmu *pmu)
|
||||
{
|
||||
return !!(hybrid(pmu, config_mask) &
|
||||
ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE);
|
||||
}
|
||||
|
||||
extern struct event_constraint emptyconstraint;
|
||||
|
||||
extern struct event_constraint unconstrained;
|
||||
@@ -1667,6 +1695,10 @@ u64 lnl_latency_data(struct perf_event *event, u64 status);
|
||||
|
||||
u64 arl_h_latency_data(struct perf_event *event, u64 status);
|
||||
|
||||
u64 pnc_latency_data(struct perf_event *event, u64 status);
|
||||
|
||||
u64 nvl_latency_data(struct perf_event *event, u64 status);
|
||||
|
||||
extern struct event_constraint intel_core2_pebs_event_constraints[];
|
||||
|
||||
extern struct event_constraint intel_atom_pebs_event_constraints[];
|
||||
@@ -1679,6 +1711,8 @@ extern struct event_constraint intel_glp_pebs_event_constraints[];
|
||||
|
||||
extern struct event_constraint intel_grt_pebs_event_constraints[];
|
||||
|
||||
extern struct event_constraint intel_arw_pebs_event_constraints[];
|
||||
|
||||
extern struct event_constraint intel_nehalem_pebs_event_constraints[];
|
||||
|
||||
extern struct event_constraint intel_westmere_pebs_event_constraints[];
|
||||
@@ -1699,6 +1733,8 @@ extern struct event_constraint intel_glc_pebs_event_constraints[];
|
||||
|
||||
extern struct event_constraint intel_lnc_pebs_event_constraints[];
|
||||
|
||||
extern struct event_constraint intel_pnc_pebs_event_constraints[];
|
||||
|
||||
struct event_constraint *intel_pebs_constraints(struct perf_event *event);
|
||||
|
||||
void intel_pmu_pebs_add(struct perf_event *event);
|
||||
|
||||
@@ -259,6 +259,11 @@
|
||||
#define MSR_SNOOP_RSP_0 0x00001328
|
||||
#define MSR_SNOOP_RSP_1 0x00001329
|
||||
|
||||
#define MSR_OMR_0 0x000003e0
|
||||
#define MSR_OMR_1 0x000003e1
|
||||
#define MSR_OMR_2 0x000003e2
|
||||
#define MSR_OMR_3 0x000003e3
|
||||
|
||||
#define MSR_LBR_SELECT 0x000001c8
|
||||
#define MSR_LBR_TOS 0x000001c9
|
||||
|
||||
|
||||
@@ -33,6 +33,7 @@
|
||||
#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
|
||||
#define ARCH_PERFMON_EVENTSEL_BR_CNTR (1ULL << 35)
|
||||
#define ARCH_PERFMON_EVENTSEL_EQ (1ULL << 36)
|
||||
#define ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE (1ULL << 37)
|
||||
#define ARCH_PERFMON_EVENTSEL_UMASK2 (0xFFULL << 40)
|
||||
|
||||
#define INTEL_FIXED_BITS_STRIDE 4
|
||||
@@ -40,6 +41,7 @@
|
||||
#define INTEL_FIXED_0_USER (1ULL << 1)
|
||||
#define INTEL_FIXED_0_ANYTHREAD (1ULL << 2)
|
||||
#define INTEL_FIXED_0_ENABLE_PMI (1ULL << 3)
|
||||
#define INTEL_FIXED_0_RDPMC_USER_DISABLE (1ULL << 33)
|
||||
#define INTEL_FIXED_3_METRICS_CLEAR (1ULL << 2)
|
||||
|
||||
#define HSW_IN_TX (1ULL << 32)
|
||||
@@ -50,7 +52,7 @@
|
||||
#define INTEL_FIXED_BITS_MASK \
|
||||
(INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER | \
|
||||
INTEL_FIXED_0_ANYTHREAD | INTEL_FIXED_0_ENABLE_PMI | \
|
||||
ICL_FIXED_0_ADAPTIVE)
|
||||
ICL_FIXED_0_ADAPTIVE | INTEL_FIXED_0_RDPMC_USER_DISABLE)
|
||||
|
||||
#define intel_fixed_bits_by_idx(_idx, _bits) \
|
||||
((_bits) << ((_idx) * INTEL_FIXED_BITS_STRIDE))
|
||||
@@ -226,7 +228,9 @@ union cpuid35_ebx {
|
||||
unsigned int umask2:1;
|
||||
/* EQ-bit Supported */
|
||||
unsigned int eq:1;
|
||||
unsigned int reserved:30;
|
||||
/* rdpmc user disable Supported */
|
||||
unsigned int rdpmc_user_disable:1;
|
||||
unsigned int reserved:29;
|
||||
} split;
|
||||
unsigned int full;
|
||||
};
|
||||
|
||||
@@ -1311,14 +1311,16 @@ union perf_mem_data_src {
|
||||
mem_snoopx : 2, /* Snoop mode, ext */
|
||||
mem_blk : 3, /* Access blocked */
|
||||
mem_hops : 3, /* Hop level */
|
||||
mem_rsvd : 18;
|
||||
mem_region : 5, /* cache/memory regions */
|
||||
mem_rsvd : 13;
|
||||
};
|
||||
};
|
||||
#elif defined(__BIG_ENDIAN_BITFIELD)
|
||||
union perf_mem_data_src {
|
||||
__u64 val;
|
||||
struct {
|
||||
__u64 mem_rsvd : 18,
|
||||
__u64 mem_rsvd : 13,
|
||||
mem_region : 5, /* cache/memory regions */
|
||||
mem_hops : 3, /* Hop level */
|
||||
mem_blk : 3, /* Access blocked */
|
||||
mem_snoopx : 2, /* Snoop mode, ext */
|
||||
@@ -1375,7 +1377,7 @@ union perf_mem_data_src {
|
||||
#define PERF_MEM_LVLNUM_L4 0x0004 /* L4 */
|
||||
#define PERF_MEM_LVLNUM_L2_MHB 0x0005 /* L2 Miss Handling Buffer */
|
||||
#define PERF_MEM_LVLNUM_MSC 0x0006 /* Memory-side Cache */
|
||||
/* 0x007 available */
|
||||
#define PERF_MEM_LVLNUM_L0 0x0007 /* L0 */
|
||||
#define PERF_MEM_LVLNUM_UNC 0x0008 /* Uncached */
|
||||
#define PERF_MEM_LVLNUM_CXL 0x0009 /* CXL */
|
||||
#define PERF_MEM_LVLNUM_IO 0x000a /* I/O */
|
||||
@@ -1428,6 +1430,25 @@ union perf_mem_data_src {
|
||||
/* 5-7 available */
|
||||
#define PERF_MEM_HOPS_SHIFT 43
|
||||
|
||||
/* Cache/Memory region */
|
||||
#define PERF_MEM_REGION_NA 0x0 /* Invalid */
|
||||
#define PERF_MEM_REGION_RSVD 0x01 /* Reserved */
|
||||
#define PERF_MEM_REGION_L_SHARE 0x02 /* Local CA shared cache */
|
||||
#define PERF_MEM_REGION_L_NON_SHARE 0x03 /* Local CA non-shared cache */
|
||||
#define PERF_MEM_REGION_O_IO 0x04 /* Other CA IO agent */
|
||||
#define PERF_MEM_REGION_O_SHARE 0x05 /* Other CA shared cache */
|
||||
#define PERF_MEM_REGION_O_NON_SHARE 0x06 /* Other CA non-shared cache */
|
||||
#define PERF_MEM_REGION_MMIO 0x07 /* MMIO */
|
||||
#define PERF_MEM_REGION_MEM0 0x08 /* Memory region 0 */
|
||||
#define PERF_MEM_REGION_MEM1 0x09 /* Memory region 1 */
|
||||
#define PERF_MEM_REGION_MEM2 0x0a /* Memory region 2 */
|
||||
#define PERF_MEM_REGION_MEM3 0x0b /* Memory region 3 */
|
||||
#define PERF_MEM_REGION_MEM4 0x0c /* Memory region 4 */
|
||||
#define PERF_MEM_REGION_MEM5 0x0d /* Memory region 5 */
|
||||
#define PERF_MEM_REGION_MEM6 0x0e /* Memory region 6 */
|
||||
#define PERF_MEM_REGION_MEM7 0x0f /* Memory region 7 */
|
||||
#define PERF_MEM_REGION_SHIFT 46
|
||||
|
||||
#define PERF_MEM_S(a, s) \
|
||||
(((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
|
||||
|
||||
|
||||
@@ -1311,14 +1311,16 @@ union perf_mem_data_src {
|
||||
mem_snoopx : 2, /* Snoop mode, ext */
|
||||
mem_blk : 3, /* Access blocked */
|
||||
mem_hops : 3, /* Hop level */
|
||||
mem_rsvd : 18;
|
||||
mem_region : 5, /* cache/memory regions */
|
||||
mem_rsvd : 13;
|
||||
};
|
||||
};
|
||||
#elif defined(__BIG_ENDIAN_BITFIELD)
|
||||
union perf_mem_data_src {
|
||||
__u64 val;
|
||||
struct {
|
||||
__u64 mem_rsvd : 18,
|
||||
__u64 mem_rsvd : 13,
|
||||
mem_region : 5, /* cache/memory regions */
|
||||
mem_hops : 3, /* Hop level */
|
||||
mem_blk : 3, /* Access blocked */
|
||||
mem_snoopx : 2, /* Snoop mode, ext */
|
||||
@@ -1375,7 +1377,7 @@ union perf_mem_data_src {
|
||||
#define PERF_MEM_LVLNUM_L4 0x0004 /* L4 */
|
||||
#define PERF_MEM_LVLNUM_L2_MHB 0x0005 /* L2 Miss Handling Buffer */
|
||||
#define PERF_MEM_LVLNUM_MSC 0x0006 /* Memory-side Cache */
|
||||
/* 0x007 available */
|
||||
#define PERF_MEM_LVLNUM_L0 0x0007 /* L0 */
|
||||
#define PERF_MEM_LVLNUM_UNC 0x0008 /* Uncached */
|
||||
#define PERF_MEM_LVLNUM_CXL 0x0009 /* CXL */
|
||||
#define PERF_MEM_LVLNUM_IO 0x000a /* I/O */
|
||||
@@ -1428,6 +1430,25 @@ union perf_mem_data_src {
|
||||
/* 5-7 available */
|
||||
#define PERF_MEM_HOPS_SHIFT 43
|
||||
|
||||
/* Cache/Memory region */
|
||||
#define PERF_MEM_REGION_NA 0x0 /* Invalid */
|
||||
#define PERF_MEM_REGION_RSVD 0x01 /* Reserved */
|
||||
#define PERF_MEM_REGION_L_SHARE 0x02 /* Local CA shared cache */
|
||||
#define PERF_MEM_REGION_L_NON_SHARE 0x03 /* Local CA non-shared cache */
|
||||
#define PERF_MEM_REGION_O_IO 0x04 /* Other CA IO agent */
|
||||
#define PERF_MEM_REGION_O_SHARE 0x05 /* Other CA shared cache */
|
||||
#define PERF_MEM_REGION_O_NON_SHARE 0x06 /* Other CA non-shared cache */
|
||||
#define PERF_MEM_REGION_MMIO 0x07 /* MMIO */
|
||||
#define PERF_MEM_REGION_MEM0 0x08 /* Memory region 0 */
|
||||
#define PERF_MEM_REGION_MEM1 0x09 /* Memory region 1 */
|
||||
#define PERF_MEM_REGION_MEM2 0x0a /* Memory region 2 */
|
||||
#define PERF_MEM_REGION_MEM3 0x0b /* Memory region 3 */
|
||||
#define PERF_MEM_REGION_MEM4 0x0c /* Memory region 4 */
|
||||
#define PERF_MEM_REGION_MEM5 0x0d /* Memory region 5 */
|
||||
#define PERF_MEM_REGION_MEM6 0x0e /* Memory region 6 */
|
||||
#define PERF_MEM_REGION_MEM7 0x0f /* Memory region 7 */
|
||||
#define PERF_MEM_REGION_SHIFT 46
|
||||
|
||||
#define PERF_MEM_S(a, s) \
|
||||
(((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
|
||||
|
||||
|
||||
@@ -939,6 +939,7 @@ static bool perf_pmu__match_wildcard(const char *pmu_name, const char *tok)
|
||||
{
|
||||
const char *p, *suffix;
|
||||
bool has_hex = false;
|
||||
bool has_underscore = false;
|
||||
size_t tok_len = strlen(tok);
|
||||
|
||||
/* Check start of pmu_name for equality. */
|
||||
@@ -949,13 +950,14 @@ static bool perf_pmu__match_wildcard(const char *pmu_name, const char *tok)
|
||||
if (*p == 0)
|
||||
return true;
|
||||
|
||||
if (*p == '_') {
|
||||
++p;
|
||||
++suffix;
|
||||
}
|
||||
|
||||
/* Ensure we end in a number */
|
||||
/* Ensure we end in a number or a mix of number and "_". */
|
||||
while (1) {
|
||||
if (!has_underscore && (*p == '_')) {
|
||||
has_underscore = true;
|
||||
++p;
|
||||
++suffix;
|
||||
}
|
||||
|
||||
if (!isxdigit(*p))
|
||||
return false;
|
||||
if (!has_hex)
|
||||
|
||||
Reference in New Issue
Block a user